This paper provides algorithms in order to solve an interval implicit function of the Poincare map generated by a continuous piece-wise linear (CPWL) vector field, with the use of interval arithmetic. The algorithms are implemented with the use of MATLAB and INTLAB. We present an application to verification of canards in two-dimensional CPWL vector field appearing in nonlinear piecewise linear circuits frequently, and confirm that the algorithms are effective.

This paper newly proposes a method to automatically decompose real scene images into multiple object-oriented component regions. First, histogram patterns of a specific image feature, such as intensity or hue value, are estimated from image sequence and stored up. Next, Gaussian distribution parameters which correspond to object components involved in the scene are estimated by applying the EM algorithm to the accumulated histogram. The number of the components is simultaneously estimated by evaluating the minimum value of Bayesian Information Criterion (BIC). This method can be applied to a variety of computer vision issues, for example, the color image segmentation and the recognition of scene situation transition. Experimental results applied for indoor and outdoor scenes showed the effectiveness of the proposed method.

In this paper, rail-to-rail OTA utilizing linear V-I conversion circuit whose input stage is composed of single channel MOSFETs, is proposed. The proposed conversion circuit is realized with two circuit blocks. One of them consists of a single MOSFET operating in plural regions and the other a pair of MOSFETs in saturation region and cut-off region. Combination of the circuit blocks achieves a linear voltage-current conversion for a rail-to-rail input signal. Rail-to-rail OTA is proposed using the proposed conversion circuit. HSPICE simulations are performed to verify the validity of the proposed V-I converter and rail-to-rail OTA. Simulation results indicate good performances. As an application example, 2nd-order LPF is realized using the proposed OTAs.

This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.

We propose a method of controlling the view divergence of data freshness when copies of sites in a replicated database are updated asynchronously. The view divergence of the replicated data freshness is the difference in the recentness of the updates reflected in the data acquired by clients. Our method accesses multiple sites and provides a client with data that reflects all the updates received by the sites. First, we define the probabilistic recentness of updates reflected in acquired data as read data freshness (RDF). The degree of RDF of data acquired by clients is the range of view divergence. Second, we propose a way to select sites in a replicated database by using the probability distribution of the update delays so that the data acquired by a client satisfies its required RDF. This way calculates the minimum number of sites in order to reduce the overhead of read transactions. Our method continues to adaptively and reliably provide data that meets the client's requirements in an environment where the delay of update propagation varies and applications' requirements change depending on the situation. Finally, we evaluate by simulation the view divergence we can control using our method. The simulation showed that our method can control the view divergence to about 1/4 that of a normal read transaction for 100 replicas. In addition, the increase in the overhead of a read transaction imposed by our method is not as much as the increase in the total number of replicas.

VLSI architecture of IEEE802.11i cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.11a/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with 18 Kgates in 0.18 µm CMOS technology, which achieves the maximum transmission rate of IEEE802.11a/g at 60 MHz clock frequency while consuming 14.5 mW of power.

In this paper two algorithms for the synthesis and minimization of a CA (cellular array architecture) are proposed. Starting from a completely specified single-output switching function, our methods produce rectangularly shaped arrays of cells, interconnected in chains, with an effort to minimize the number of the produced chains (cascades). This kind of cellular topology is known throughout the bibliography as Maitra cellular arrays. The significance of those algorithms is underlined by the fact that this particular type of cellular architecture can be mapped to reversible circuits and gates (generalized Toffoli gates), which are the type of logic used in quantum circuits. The proposed methodologies include use of ETDDs (EXOR ternary decision diagrams), and switching function decompositions (including new types of boolean expansions).

We have developed an estimation system of the electric parameters for liquid materials without a sensor connecting to the testing materials. A PC can be used for the calculation, and the calculation time is about 2 minutes. The accuracy is such that the estimated values are different from the nominal values by less than 2%.

A GPS radio design for a complete single chip GPS receiver using 0.18-µm CMOS is presented. The complete single chip GPS receiver satisfies several key requirements for mobile applications, such as compactness, low power, and high sensitivity. The radio part, including the RF front end, the RF/IF PLLs, and IF functions, occupies 2.0 2.3 mm in a total chip area of 6.3 6.3 mm. It is fabricated using 0.18-µm CMOS technology utilizing MIM capacitors. The radio part operates within a 1.6 to 2.0 V supply voltage range and consumes 27 mW at 1.8 V. The whole GPS SoC consumes 57 mW for a fully functional chip and provides a high sensitivity of -152 dBm. The radio design features countermeasures against substrate coupling noise from the digital part.

Recently, various types of traffic have increased on the Internet with the development of broadband networks. However, it is difficult to guarantee QoS for each traffic type in current network environments. Moreover, it has been reported that bandwidth can be allocated to flows unfairly, and this can be an important issue for QoS guarantees. Therefore, we have proposed a flow-based queue management scheme, called Dual Metrics Fair Queueing (DMFQ), to improve the fairness and QoS per flow. DMFQ discards arrival packets by considering not only the arrival rate per flow but also the flow succession time. In addition, we have confirmed the effectiveness of DMFQ through several computer simulations. In this paper, we implement DMFQ with hardware for high-speed operation. Concretely, we propose the design policies and show the hardware design results.

This paper proposes a decentralized and asynchronous replica control method based on a fair assignment of the variation in numerical data that has weak consistency for loosely coupled database systems managed or used by different organizations of human activity. Our method eliminates the asynchronous abort of already committed transactions even if replicas in all network partitions continue to process transactions when network partitioning occurs. A decentralized and asynchronous approach is needed because it is difficult to keep a number of loosely coupled systems in working order, and replica operations performed in a centralized and synchronous way can degrade the performance of transaction processing. We eliminate the transaction abort by fairly distributing the variation in numerical data to replicas according to their demands and updating the distributed variation using only asynchronously propagated update transactions without calculating the precise global state among reachable replicas. In addition, fairly assigning the variation of data to replicas equalizes the disadvantages of processing update transactions among replicas. Fairness control for assigning the data variation is performed by averaging the variation requested by the replicas. A simulation showed that our system can achieve extremely high performance for processing update transactions and fairness among replicas.

Poly-Si TFT (Thin Film transistor) fabricated below 170 using excimer laser crystallization of sputtered Si films was characterized. In particular, a gate insulator with a breakdown field exceeding 8 MV/cm was deposited by using ICP (Inductively Coupled Plasma) CVD (Chemical Vapor Deposition). A buffer layer possessing high thermal conductivity was inserted between the active channel and the plastic substrate, in order to protect the plastic substrate from the thermal energy of the laser and to increase adhesion of Si film on plastic. Using this method, we successfully fabricate TFT with a stable electron field-effect mobility value greater than 14.7 cm2/Vsec.

This note considers a problem of minimum length scheduling for a set of messages subject to precedence constraints for switching and communication networks, and shows some improvements upon previous results on the problem.

Fair scheduling algorithms have been proposed to tackle the problem of bursty and location-dependent errors in wireless packet networks. Most of those algorithms ensure the fairness property and guarantee the QoS of all sessions in a large-scale cellular network such as GSM or GPRS. In this paper, we propose the Weighted-Sacrificing Fair Queueing (WSFQ) scheduling algorithm for small-area and device-limited wireless networks. WSFQ slows down the growth of queue length in limited-buffer devices, still maintains the properties of fairness, and guarantees the throughputs of the system. Moreover, WSFQ can easily adapt itself to various kinds of traffic load. We also implement a packet-based scheduling algorithm, the Packetized Weighted Sacrificing Fair Queueing (PWSFQ), to approach the WSFQ. WSFQ and PWSFQ are evaluated by comparing with other algorithms by mathematical analysis and simulations.

This paper proposes an iterative parallel genetic algorithm with biased initial population to solve large-scale combinatorial optimization problems. The proposed scheme employs a master-slave collaboration in which the master node manages searched space of slave nodes and assigns seeds to generate initial population to slaves for their restarting of evolution process. Our approach allows us as widely as possible to search by all the slave nodes in the beginning period of the searching and then focused searching by multiple slaves on a certain spaces that seems to include good quality solutions. Computer experiment shows the effectiveness of our proposed scheme.

Dynamic power supply noise measurements with resolutions of 100 ps and 100 µV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias network's AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.

In 2002, Zhu et al. proposed a password authenticated key exchange protocol based on RSA such that it is efficient enough to be implemented on most of the target low-power devices such as smart cards and low-power Personal Digital Assistants in imbalanced wireless networks. Recently, YEH et al. claimed that Zhu et al.'s protocol not only is insecure against undetectable on-line password guessing attack but also does not achieve explicit key authentication. Thus they presented an improved version. Unfortunately, we find that YEH et al.'s password guessing attack does not come into existence, and that their improved protocol is vulnerable to off-line dictionary attacks. In this paper we describe our observation in details, and also comment for the original protocol on how to achieve explicit key authentication as well as resist against other existent attacks.

Spring-mass systems are widely used in computer animation to model soft objects. Although the systems can be numerically solved either by explicit methods or implicit methods, it has been difficult to obtain stable results from explicit methods. This paper describes detailed discussion on stabilizing explicit methods in spring-mass simulation. The simulation procedures are modeled as a linear digital system, and system stability is mathematically defined. This allows us to develop theories of simulation stability. The application of these theories to explicit methods allows them to become as stable as implicit methods. Furthermore, a faster explicit method is proposed. Experiments confirm the theories and demonstrate the efficiency of the proposed methods.

The performance of en-route web caching mainly depends on where the caches are located and how the cache contents are managed. In this paper, we address the problem of proxy placement in en-route web caching for tree networks, i.e., computing the optimal locations for placing k web proxies in a network such that some specified objectives are achieved. Based on our proposed model, we formulate this problem as an optimization problem and compute the optimal locations using a computationally efficient dynamic programming-based algorithm. We also extend our solution for tree networks to solve the same problem for autonomous systems. Finally, we implement our algorithms and evaluate our model on several performance metrics through extensive simulation experiments. We also compare the performance of our model with the best available heuristic KMPC model, as well as the random proxy placement model. The implementation results show that our model outperforms all the other models with respect to all performance metrics considered. The average improvements of our model over the KMPC model and the random proxy placement model are about 31.9 percent and 58.6 percent in terms of all the performance metrics considered.

Programmable Logic Controller (PLC) has been widely used in the industrial control. Inherently, the PLC-based system is a class of Hybrid Dynamical System (HDS) in which continuous state of the plant is controlled by the discrete logic-based controller. This paper firstly presents the formal algebraic model of the PLC-based control systems which enable the designer to formulate the various kinds of optimization problem. Secondly, the optimization problem of the 'sensor parameters,' such as the location of the limit switch in the material handling system, the threshold temperature of the thermostat in the temperature control system, is addressed. Finally, we formulate this problem as Mixed Logical Dynamical Systems (MLDS) form which enables us to optimize the sensor parameters by applying the Mixed Integer Programming.