An ultra low power CMOS SAW oscillator in the 300-MHz-band that operates on a sub-1 V supply voltage and at sub-1 mW power consumption has been developed. The SAW oscillator is fabricated in a 0.35-µm fully depleted SOI (FD-SOI) process with low voltage operation capability. The SAW oscillator is configured as a type of Colpitts oscillator but consists of 3 cascaded amplifiers instead of a single amplifier. Although the circuit configuration is quite similar to the conventional Colpitts oscillator, this proposed configuration generates an excessively high negative resistance that even exceeds the theoretical limit of the conventional one.

We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that is wasting power. The performance per power (P3) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90 nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P3 in the future 25 nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180 nm process. It is functional at 100 MHz clock speed and its power is 130 mW.

In this paper, we present a set of sequence pairs which produce zero correlation windows not only in the middle part of the sum of aperiodic correlation functions, but also in the two terminal parts. We name it "Ear Windows." In approximately synchronous CDMA communication system, this set of sequences is able to completely remove the inter-symbol interference (ISI) and multi-user interference (MUI) caused by the multi-path effect if the maximum delay is shorter than the length of the "Ear windows." In addition, it is also feasible in M-ary modulation. The inter-code interference will be mitigated drastically.

The role of electric field in metal-induced lateral crystallization (MILC) of amorphous Si (a-Si) under limited Ni-supply condition has been investigated. The nominal lateral-growth rate was increased from 3.6 µm/h (no-electric field) to 23 µm/h at the positive electrode side and reduced to 2.8 µm/h at the negative electrode side in presence of the electric field of 20 V/cm. However, spontaneously nucleated needle-like Si crystals were observed in the enhanced positive electrode side, which have been found to be independent of the MILC. Further investigation under the condition where Ni in the supply region was removed on the way of crystallization revealed that the electric field enhanced crystallization greatly reduced. These results indicate that the electric field does not enhance the MILC growth but enhances the diffusion of Ni in a-Si which takes place prior to the MILC growth.

A new hybrid method for characterizing the irregular power/ground plane pair is developed in this paper by combining the conventional eigen-mode expansion method with the new-presented inverted composition method and a simple model order reduction. By the approach, the eigen-mode expansion method can be extended to the characteristics research of the power/ground plane pair with holes. In this gridless method, ports and decoupling capacitors can be arbitrarily placed on the plane pair. The numerical example demonstrates its good validity.

We have developed separation by bonding Si islands (SBSI) process for advanced CMOS LSI applications. In this process, the Si islands that become the SOI regions are formed by selective etching of the SiGe layer in the Si/SiGe stacked layers, and those are bonded to the Si substrate with the thermal oxide layers by furnace annealing. The etching selectivity for SiGe/Si and surface roughness after the SiGe etching were found to be improved by decreasing the HNO3 concentration in the etching solution. The thicknesses of the fabricated Si island and the buried oxide layer also became uniform by decreasing the HNO3 concentration. In addition, it was found that the space formed by SiGe etching in the Si/SiGe stacked layers was able to be filled with the thermal oxide layer without furnace annealing.

This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.

A direct tunneling memory (DTM) with ultra-thin tunnel oxide and depleted floating gate has been proposed for low power embedded RAM. To achieve excellent charge retention characteristics with ultra-thin tunnel oxide, floating gate depletion is adopted to utilize the band bending at the interface between floating gate and tunnel oxide in charge retention period. The depleted floating gate is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. These effects were evaluated by the device and process simulations and confirmed by the experimental data. As a consequence, both fast programming time and superior retention time have been achieved, which is a promising performance as a low power embedded RAM for system-on-a-chip (SoC) applications.

This paper describes a speed-oriented ultralow-voltage and low-power SOI circuit technique based on a differential enhancement- and depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-Vth CMOS circuit block for noncritical paths, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to achieve low-power and ultrahigh-speed operation of over 1 GHz at a supply voltage of less than 0.5 V. As two applications of the differential ED-CMOS/SOI circuit, a multi-stage frequency divider that uses the ED-MOS circuit in a first-stage frequency divider and a pipelined adder with a CMOS pipeline register are described in detail. To verify the effectiveness of the ED-CMOS/SOI circuit scheme, we fabricated a 1/8 frequency divider and a 32-bit binary look-ahead carry (BLC) adder using the 0.25-µm MTCMOS/SOI process. The frequency divider operates down to 0.3 V with a maximum operating frequency of 3.6 GHz while suppressing power dissipation to 0.3 mW. The 32-bit adder operates at a frequency of 1 GHz at 0.5 V.

A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i. e. , table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-µm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.8% of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE.

This paper describes a sub-1-V power-supply, which is useful for self-powered short-range wireless systems with ambient energy sources. A variable-stage DC-DC converter, which consists of multi-stage switched capacitor circuits and has intermittent operation with an external capacitor, makes it possible to extend the time for self-powered operation. We fabricated a variable-stage DC-DC converter and an intermittent operation circuit with a 0.8-µm CMOS/SOI process. We also applied the sub-1-V power-supply system to a self-powered short-range wireless system and verified its effectiveness.

The DNSSECbis data model has key introduction follow the delegation chain, thus requiring a zone's parent to become secure before a zone itself can be secured. Ultimately this leads to non-deployability since the root zone will probably not be secured any time soon. We describe an early deployment aid for DNSSECbis whereby key introduction can be done via cooperating third parties.

In this report, we propose a tracking algorithm of speaker direction using microphones located at vertices of an equilateral triangle. The method realizes tracking by minimizing a performance index that consists of the cross spectra at three different microphone pairs in the triangular array. We adopt the steepest descent method to minimize it, and for guaranteeing global convergence to the correct direction with high accuracy, we alter the performance index during the adaptation depending on the convergence state. Through some computer simulation and experiments in a real acoustic environment, we show the effectiveness of the proposed method.

This paper proposes a new effective data transfer method for IEEE 802.11 wireless LANs by integrating priority control and multirate mechanism. The IEEE 802.11 PHY layer supports a multirate mechanism with dynamic rate switching and an appropriate data rate is selected in transmitting a frame. However, the multirate mechanism is used with the CSMA/CA (Carrier Sense Multiple Access with Collision Avoidance) protocol, low rate transmissions need much longer time than high rate transmissions to finish sending a frame. As a result, the system capacity is decreased. The proposed method assumes the same number of priority levels as the data rates, and a data rate is associated to a priority level. Priority of a transmission goes up with the used data rate. For this purpose, we have modified the CSMA/CA protocol to support prioritized transmission. By selecting the appropriate priority depending on the data rate and giving more transmission opportunities for high rate transmission, the system capacity is increased. The effect of the proposed mechanism is confirmed by computer simulations.

Limited energy is a big challenge for large scale wireless sensor networks (WSN). Previous research works show that modulation scaling is an efficient technique to reduce energy consumption. However, the impacts of using modulation scaling on packet delivery latency and loss are not considered, which may have adverse effects on the application qualities. In this paper, we study this problem and propose control schemes to minimize energy consumption while ensuring application qualities. We first analyze the relationships of modulation scaling and energy consumption, end-to-end delivery latency and packet loss ratio. With the analytical model, we develop a centralized control scheme to adaptively adjust the modulation levels, in order to minimize energy consumption and ensure the application qualities. To improve the scalability of the centralized control scheme, we also propose a distributed control scheme. In this scheme, the sink will send the differences between the required and measured application qualities to the sensors. The sensors will update their modulation levels with the local information and feedback from the sink. Experimental results show the effectiveness of energy saving and QoS guarantee of the control schemes. The control schemes can adapt efficiently to the time-varying requirements on application qualities.

Synthetic speech usually suffers from bad F0 contour surface. The prediction of the underlying pitch targets robustly relies on the quality of the predicted prosodic structures, i.e. the corresponding sequences of tones and breaks. In the present work, we have utilized a linguistically enriched annotated corpus to build data-driven models for predicting prosodic structures with increased accuracy. We have then used a linear regression approach for the F0 modeling. An appropriate XML annotation scheme has been introduced to encode syntax, grammar, new or already given information, phrase subject/object information, as well as rhetorical elements in the corpus, by exploiting a Natural Language Generator (NLG) system. To prove the benefits from the introduction of the enriched input meta-information, we first show that while tone and break CART predictors have high accuracy when standing alone (92.35% for breaks, 87.76% for accents and 99.03% for endtones), their application in the TtS chain degrades the Linear Regression pitch target model. On the other hand, the enriched linguistic meta-information minimizes errors of models leading to a more natural F0 surface. Both objective and subjective evaluation were adopted for the intonation contours by taking into account the propagated errors introduced by each model in the synthesis chain.

In this paper, we propose a spatio-temporal equalizer for the space-time block coded transmission over the frequency selective fading channels with the presence of co-channel interference (CCI). The proposed equalizer, based on the tapped delay line adaptive array (TDLAA), performs signal equalization and CCI suppression simultaneously using the minimum mean square error (MMSE) method. It is to show that our scheme outperforms the previous two-stage combined adaptive antenna and delayed decision feedback sequence estimator (DDFSE) approach. We also show that performance can be further improved if the synchronization between the preceding and delayed paths is achieved.

This letter presents two methods of modeling phoneme durations. One is the context-independent phoneme duration modeling in which duration parameters are stored in each phoneme. The other is the context-dependent duration modeling in which duration parameters are stored in each state shared by context-dependent phonemes. The phoneme duration model is compared with a without-duration model and a state duration model. Experiments are performed on a database collected over the telephone network. Experimental results show that duration information rejects out-of-task (OOT) words well and that the context-dependent duration model yields the best performance among the tested models.

The phase noise has a significant effect on the M-ary PSK transmission signal, furthermore the higher-order modulation signal can not be recovered in the presence of phase noise. It is important to define exactly what is required in terms of phase noise within a particular system and to avoid expensive over-specification. Based on the analysis of allowable signal-to-noise ratio for phase reference and required phase error variance for M-ary PSK systems relative to a degradation loss objective, the general phase noise allocation method for M-ary PSK satellite communication systems has been proposed in this paper. The phase noise allocation using the proposed method is adopted for M-ary PSK multi-mode satellite communication systems. Using the oscillator phase noise model and the phase noise model of a frequency synthesizer, the required phase noise spectrum distributions are carried out and the validities of the allocated phase noise spectrums are verified by the system simulation.

A waveguide crossed-slot linear array with a matching element is accurately analyzed and designed by the method of moments using numerical-eigenmode basis functions developed by the authors. The rounded ends of crossed-slots are accurately modeled in the analysis. The initial values of the slot parameters determined by a model with assumption of periodicity of field are modified and refined by the full-wave finite-array analysis for uniform excitation and small axial ratio. As an example, an 8-element linear array is designed at 11.85 GHz, which radiates a circularly polarized wave at a beam-tilting angle of 50 degrees. The radiation pattern, the frequency characteristics of the reflection and the axial ratio are compared between the analysis and the measurement and they agree very well. The calculated and measured axial ratio at the beam direction are 0.1 dB and 1.7 dB, respectively. This method provides a basic and powerful design tool for slotted waveguide arrays.