A new hybrid method for characterizing the irregular power/ground plane pair is developed in this paper by combining the conventional eigen-mode expansion method with the new-presented inverted composition method and a simple model order reduction. By the approach, the eigen-mode expansion method can be extended to the characteristics research of the power/ground plane pair with holes. In this gridless method, ports and decoupling capacitors can be arbitrarily placed on the plane pair. The numerical example demonstrates its good validity.

This paper presents an approach of logic mapping into LUT-Array-Based PLD where Boolean functions in the form of the sum of generalized complex terms (SGCTs) can be mapped directly. While previous mapping approach requires predetermined variable ordering, our approach performs mapping and variable reordering simultaneously. For the purpose, we propose a directed acyclic graph based on the multiple-valued decision diagram (MDD) and an algorithm to construct the graph. Our algorithm generates candidates of SGCT expressions for each node in a bottom-up manner and selects the variables in the current level by evaluating the sizes of SGCT expressions directly. Experimental results show that our approach reduces the number of terms maximum to 71 percent for the MCNC benchmark circuits.

A GPS radio design for a complete single chip GPS receiver using 0.18-µm CMOS is presented. The complete single chip GPS receiver satisfies several key requirements for mobile applications, such as compactness, low power, and high sensitivity. The radio part, including the RF front end, the RF/IF PLLs, and IF functions, occupies 2.0 2.3 mm in a total chip area of 6.3 6.3 mm. It is fabricated using 0.18-µm CMOS technology utilizing MIM capacitors. The radio part operates within a 1.6 to 2.0 V supply voltage range and consumes 27 mW at 1.8 V. The whole GPS SoC consumes 57 mW for a fully functional chip and provides a high sensitivity of -152 dBm. The radio design features countermeasures against substrate coupling noise from the digital part.

VLSI architecture of IEEE802.11i cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.11a/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with 18 Kgates in 0.18 µm CMOS technology, which achieves the maximum transmission rate of IEEE802.11a/g at 60 MHz clock frequency while consuming 14.5 mW of power.

This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.

We propose a method of controlling the view divergence of data freshness when copies of sites in a replicated database are updated asynchronously. The view divergence of the replicated data freshness is the difference in the recentness of the updates reflected in the data acquired by clients. Our method accesses multiple sites and provides a client with data that reflects all the updates received by the sites. First, we define the probabilistic recentness of updates reflected in acquired data as read data freshness (RDF). The degree of RDF of data acquired by clients is the range of view divergence. Second, we propose a way to select sites in a replicated database by using the probability distribution of the update delays so that the data acquired by a client satisfies its required RDF. This way calculates the minimum number of sites in order to reduce the overhead of read transactions. Our method continues to adaptively and reliably provide data that meets the client's requirements in an environment where the delay of update propagation varies and applications' requirements change depending on the situation. Finally, we evaluate by simulation the view divergence we can control using our method. The simulation showed that our method can control the view divergence to about 1/4 that of a normal read transaction for 100 replicas. In addition, the increase in the overhead of a read transaction imposed by our method is not as much as the increase in the total number of replicas.

We propose a novel approach for designing a low power datapath in wireless communication systems. Especially, we focus on the digital FIR filter. Our proposed approach can reduce the power consumption and the circuit area of the digital FIR filter by optimizing the bitwidth of the each filter coefficient with keeping the filter calculation accuracy. At first, we formulate the constraints about keeping accuracy of the filter calculations. We define the problem to find the optimized bitwidth of each filter coefficient. Our defined problem can be solved by using the commercial optimization tool. We evaluate the effects of consuming power reduction by comparing the digital FIR filters designed in the same bitwidth of all coefficients. We confirm that our approach is effective for a low power digital FIR filter.

Programmable Logic Controller (PLC) has been widely used in the industrial control. Inherently, the PLC-based system is a class of Hybrid Dynamical System (HDS) in which continuous state of the plant is controlled by the discrete logic-based controller. This paper firstly presents the formal algebraic model of the PLC-based control systems which enable the designer to formulate the various kinds of optimization problem. Secondly, the optimization problem of the 'sensor parameters,' such as the location of the limit switch in the material handling system, the threshold temperature of the thermostat in the temperature control system, is addressed. Finally, we formulate this problem as Mixed Logical Dynamical Systems (MLDS) form which enables us to optimize the sensor parameters by applying the Mixed Integer Programming.

A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.

In this paper two algorithms for the synthesis and minimization of a CA (cellular array architecture) are proposed. Starting from a completely specified single-output switching function, our methods produce rectangularly shaped arrays of cells, interconnected in chains, with an effort to minimize the number of the produced chains (cascades). This kind of cellular topology is known throughout the bibliography as Maitra cellular arrays. The significance of those algorithms is underlined by the fact that this particular type of cellular architecture can be mapped to reversible circuits and gates (generalized Toffoli gates), which are the type of logic used in quantum circuits. The proposed methodologies include use of ETDDs (EXOR ternary decision diagrams), and switching function decompositions (including new types of boolean expansions).

We have developed an estimation system of the electric parameters for liquid materials without a sensor connecting to the testing materials. A PC can be used for the calculation, and the calculation time is about 2 minutes. The accuracy is such that the estimated values are different from the nominal values by less than 2%.

In this paper, rail-to-rail OTA utilizing linear V-I conversion circuit whose input stage is composed of single channel MOSFETs, is proposed. The proposed conversion circuit is realized with two circuit blocks. One of them consists of a single MOSFET operating in plural regions and the other a pair of MOSFETs in saturation region and cut-off region. Combination of the circuit blocks achieves a linear voltage-current conversion for a rail-to-rail input signal. Rail-to-rail OTA is proposed using the proposed conversion circuit. HSPICE simulations are performed to verify the validity of the proposed V-I converter and rail-to-rail OTA. Simulation results indicate good performances. As an application example, 2nd-order LPF is realized using the proposed OTAs.

Global computing system (GCS) harnesses the idle CPU resources of clients connected to Internet for solving large problems that require high volume of computing power. Since GCS scale to millions of clients, many projects usually adopt coarse-grained scheduling in order to reduce server-side contention at the expense of sacrificing the degree of parallelism and wasting CPU resources. In this paper, we propose a new type of client, i.e., a scheduling proxy that enables adaptive-grained scheduling between the server and clients. While the server allocates coarse-grained work units to scheduling proxies alone, clients download fine-grained work units from a relatively nearby scheduling proxy not from the distant server. By computation of small work units at client side, the turnaround time of work unit can be reduced and the waste of CPU time by timeout can be minimized without increasing the performance cost of contention at the server. In addition, in order not to lose results in the failure of scheduling proxies, we suggest a technique of result caching in clients.

This paper provides algorithms in order to solve an interval implicit function of the Poincare map generated by a continuous piece-wise linear (CPWL) vector field, with the use of interval arithmetic. The algorithms are implemented with the use of MATLAB and INTLAB. We present an application to verification of canards in two-dimensional CPWL vector field appearing in nonlinear piecewise linear circuits frequently, and confirm that the algorithms are effective.

The linear operation of a HBT with a GaAs/InGaP composite collector structure is demonstrated. The composite collector structure allows for a thin collector design that is suitable for the linear operation of a HBT without critical degradation of the breakdown voltage. The load pull measurements under a 1.95 GHz WCDMA signal have shown that a composite-collector HBT with a 400-nm thick collector layer operates with power-added-efficiency (PAE) as high as 53% at VCE = 3.5 V as a result of improved distortion characteristics. Despite the thin collector design, collector-emitter breakdown voltage of 11 V was achieved even at current density of 10 kA/cm2. The composite-collector HBT has even greater advantage for future low voltage (< 3 V) applications where maintaining PAE and linearity becomes one of the critical issues.

We have fabricated poly-Si/Si0.7Ge0.3/Si stacked gate on 4 nm-thick SiO2/Si(100), and examined the diffusion of Ge and impurities as a function of annealing temperature in the range of 800-1000 by energy dispersive X-ray spectroscopy (EDX) and secondary ion mass spectrometry (SIMS). It is reviealed that germanium atoms diffuse into 100 nm-thick silicon cap layer uniformly after 1000 annealing for 30 min and the crystallinity of As+ doped poly-SiGe is better than that of doped poly-SiGe. Also, in comparison with poly-Si gate MOS capacitors, we have confirmed that MOS capcitors with p+ and n+ SiGe gates show a 0.2 V reduction in the flat-band voltage for p+ gate and no change for n+ gate, with no increase in gate leakage current with respect to the oxide voltage. This result is attributable to the difference in the energy band structure between Si and Si0.7Ge0.3.

This paper newly proposes a method to automatically decompose real scene images into multiple object-oriented component regions. First, histogram patterns of a specific image feature, such as intensity or hue value, are estimated from image sequence and stored up. Next, Gaussian distribution parameters which correspond to object components involved in the scene are estimated by applying the EM algorithm to the accumulated histogram. The number of the components is simultaneously estimated by evaluating the minimum value of Bayesian Information Criterion (BIC). This method can be applied to a variety of computer vision issues, for example, the color image segmentation and the recognition of scene situation transition. Experimental results applied for indoor and outdoor scenes showed the effectiveness of the proposed method.

This paper presents two new intelligent methods to linearize the Multi-Carrier Power Amplifiers (MCPA). One of the them is based on the Neuro-Fuzzy controller while the other uses two small neural networks as a polar predistorter. Neuro-Fuzzy controllers are not model based, and hence, have ability to control the nonlinear systems with undetermined parameters. Both methods are adaptive, low complex, and can be implemented in base-band part of the communication systems. The performance of the linearizers is obtained via simulation. The simulation is performed for three different scenarios; namely, a multi-carrier amplifier for GSM with four channels, a CDMA amplifier and a multi-carrier amplifier with two tones. The simulation results show that Neuro-Fuzzy Controller (NFC) and Neural Network Polar Predistorter (NNPP) have higher efficiencies so that reduce IMD3 by more than 42 and 32 dB, respectively. The practical implementation aspects of these methods are also discussed in this paper.

This letter presents a reduction technique of penetrated electromagnetic fields through a narrow slot in a planar conducting screen. When a plane wave is excited to the narrow slot, the aperture electric field is controlled by the two parallel wires connected on the slot. The magnitude of penetrated electromagnetic fields through a narrow slot is controlled by electric field distributions on the slot aperture. The results show that the magnitude of the penetrated electromagnetic field can be effectively reduced by installing the two parallel wires on the slot.

In this letter, pilot-assisted adaptive prediction iterative channel estimation in frequency-domain is presented for the antenna diversity reception of orthogonal frequency division multiplexing (OFDM) signals. A frequency-domain adaptive prediction filtering is applied to iterative channel estimation for improving the tracking capability against frequency-domain variations in a severe frequency-selective fading channel. Also, in order to track the changing fading environment, the tap weights of frequency-domain prediction filter are updated using the simple NLMS algorithm. Updating of tap weights is incorporated into the iterative channel estimation loop to achieve faster convergence rate. The average bit error rate (BER) performance in a frequency-selective Rayleigh fading channel is evaluated by computer simulation. It is confirmed that the frequency-domain adaptive prediction iterative channel estimation provides better BER performance than the conventional iterative channel estimation schemes.