In this paper, performance of chaos and burst noises injected to the Hopfield Neural Network for quadratic assignment problems is investigated. For the evaluation of the noises, two methods to appreciate finding a lot of nearly optimal solutions are proposed. By computer simulations, it is confirmed that the burst noise generated by the Gilbert model with a laminar part and a burst part achieved the good performance as the intermittency chaos noise near the three-periodic window.

A multiple channel active noise control (ANC) system with several secondary sources, error sensors, and reference sensors has been used for complicated noise fields. Centralized multiple channel ANC systems have been proposed, however implementation of such systems becomes difficult according to increase of control points. Distributed multiple channel ANC systems which have more than a controller are considered. This paper proposes a new implementation of distributed multiple channel ANC systems based on simultaneous equations methods. In the proposed algorithm, communications between controllers are permitted to distribute the computational burden and to improve the performance of noise reduction. This algorithm shows good performances for noise cancellation and tracking of changes in the error paths.

A vibration-to-electric energy converter as a power generator through a variable-resonating capacitor is theoretically and experimentally demonstrated as a potential on-chip battery. The converter is constructed from three components: a mechanical-variable capacitor, a charge-transporter circuit and a timing-capture control circuit. An optimum design methodology is theoretically described to maximize the efficiency of the vibration-to-electric energy conversion. The energy-conversion efficiency is analyzed based on the following three factors: the mechanical-energy to electric-energy conversion loss, the parasitic elements loss in the charge-transporter circuit and the timing error in the timing-capture circuit. Through the mechanical-energy conversion analysis, the optimum condition for the resonance is found. The parasitic elements in the charge-transporter circuit and the timing management of the capture circuit dominate the output energy efficiency. These analyses enable the optimum design of the energy-conversion system. The converter is fabricated experimentally. The practical measured power is 0.12 µW, and the conversion efficiency is 21%. This efficiency is calculated from a 43% mechanical-energy conversion loss and a 63% charge-transportation loss. The timing-capture circuit is manually controlled in this experiment, so that the timing error is not considered in the efficiency. From our result, a new system LSI application with an embedded power source can be explored for the ubiquitous computing world.

Turbo codes are of particular use in applications of wireless communication systems, where various types of communication are required and the data rate must be changed, depending on the situation. In such applications, adaptation of turbo coding specifications is required in terms of coding block size, data speed, parity bit arrangement or configuration of a convolutional coder, as well as the need for real time processing. We present new ideas to provide these capabilities for a low power decoder circuit by focusing on the configuration of a convolutional decoding algorithm, which occupies a significant proportion of the hardware circuit. We utilize the Soft Output Viterbi Algorithm (SOVA) for the base algorithm, produced by adding the concept of a soft output to the Viterbi Algorithm (VA). The Maximum A Posteriori (MAP) algorithm and its simplified version of MAX-LOG-MAP are also widely known. MAP is recognized as a means of achieving very good bit error rate (BER) characteristics. On the other hand SOVA has been regarded as a method which can be simply implemented with less computational resources, but at a cost of higher degradation. However, in many of recent systems we combine turbo coding with some other method such as Automatic Repeat Request (ARQ) to maintain a good error correction performance and we only have to pay attention to the performance in the range of low carrier-to-noise ratio (CNR), where SOVA has fairly satisfactory BER characteristics. This makes the SOVA approach attractive for a low power programmable IP macro solution, when the fundamental advantage of SOVA is fully utilized in the implementation of an LSI circuit. We discuss the processing algorithm and circuit configuration and show that about 40% reduction in power consumption can be achieved. It is also shown that the IP macro can handle 1.5 Mbps information decoding at 100 MHz clock rate.

This paper describes an ultralow-power multi-threshold (MT) CMOS/SOI circuit technique that mainly uses fully-depleted MOSFETs. The MTCMOS/SOI circuit, which combines fully-depleted low- and medium-Vth CMOS/SOI logic gates and high-Vth power-switch transistors, makes it possible to lower the supply voltage to 0.5 V and reduce the power dissipation of LSIs to the 1-mW level. We overview some MTCMOS/SOI digital and analog components, such as a CPU, memory, analog/RF circuit and DC-DC converter for an ultralow-power mobile system. The validity of the ultralow-voltage MTCMOS/SOI circuits is confirmed by the demonstration of a self-powered 300-MHz-band short-range wireless system. A 1-V SAW oscillator and a switched-capacitor-type DC-DC converter in the transmitter makes possible self-powered transmission by the heat from a hand. In the receiver, a 0.5-V digital controller composed of a 8-bit CPU, 256-kbit SRAM, and ROM also make self-powered operation under illumination possible.

Energy dissipation in cache memories is becoming a major design issue for embedded microprocessors. Predictive filter cache based instruction cache hierarchy has been shown to effectively reduce the energy-delay product. In this paper, a simplified pattern prediction algorithm is proposed for the filter cache hierarchy. The prediction scheme relies on the static nature of the hit or miss pattern of the instruction access streams. The static patterns are maintained in a small 32x1-bit wide Static Pattern Table (SPT). Our investigations show that the proposed prediction algorithm is superior to that based on Next Fetch Prediction Table (NFPT) for all the benchmarks simulated. With the proposed approach, energy delay product reduction of up to 6.79% was evident when compared with that using NFPT. Moreover, since the prediction scheme is based on the static assignment of patterns, it lends well for area and power efficient implementation than that employs dynamic pattern prediction although it is marginally inferior (i.e. 0.69%) in term of energy delay product.

Circuit partition, retiming and state reordering techniques are effective in reducing power consumption of circuits. In this paper, we propose a partition architecture and a methodology to reduce power consumption when designing low power IP, named PRC (Partition and Reordering Circuit). The circuit reordering synthesis flow consists of three phases: first, evenly partition the circuit based on the Shannon expansion; secondly encode the output vectors of each partition to build an equivalent functional logic. Finally, apply reordering algorithm to reorganize the logic function to reduce power consumption and decrease area cost. The validity of our architecture is proven by applying it to MCNC benchmark with simulation environment.

This paper presents a Quiet-Noisy scan technique for low power delay fault testing. The novel scan cell design provides both the quiet and noisy scan modes. The toggling of scan cell outputs is suppressed in the quiet scan mode so the power is saved. Two-pattern tests are applied in the noisy scan mode so the delay fault testing is possible. The experimental data shows that the Quiet-Noisy scan technique effectively reduces the test power to 56% of that of the regular scan. The transition fault coverage is improved by 19.7% compared to an existing toggle suppression low power technique. The presented technique requires very minimal changes in the existing MUX-scan Design For Testability (DFT) methodology and needs virtually no computation. The penalties are area overhead, speed degradation, and one extra control in test mode.

Because it has desirable features such as no cascading rollback, fast output commit and asynchronous logging, causal message logging needs a consistent recovery algorithm to tolerate concurrent failures. For this purpose, Elnozahy proposed a centralized recovery algorithm to have two practical benefits, i.e. reducing the number of stable storage accesses and imposing no restriction on the execution of live processes during recovery. However, the algorithm with independent checkpointing may force the system to be in an inconsistent state when processes fail concurrently. In this paper, we identify these inconsistent cases and then present a recovery algorithm to have the two benefits and ensure the system consistency when integrated with any kind of checkpointing protocol. Also, our algorithm requires no additional message compared with Elnozahy's algorithm.

We present a novel adaptive method to improve the binarization quality of degraded word color images. The objective of this work is to solve a nonlinear problem concerning the binarization quality, that is, to achieve edge enhancement and noise reduction in images. The digitized data used in this work were extracted automatically from real world photos. The motion of objects with reference to static camera and bad environmental conditions provoked serious quality problems on those images. Conventional methods, such as the nonlinear adaptive filter method proposed by Mo, or Otsu's method cannot produce satisfactory binarization results for those types of degraded images. Among other problems, we note mainly that contrast (between shapes and backgrounds) varies greatly within every degraded image due to non-uniform illumination. The proposed method is based on the automatic extraction of background information, such as luminance distribution to adaptively control the intensity levels, that is, without the need for any manual fine-tuning of parameters. Consequently, the new method can avoid noise or inappropriate shapes in the output binary images. Otsu's method is also applied to automatic threshold selection for classifying the pixels into background and shape pixels. To demonstrate the efficiency and the feasibility of the new adaptive method, we present results obtained by the binarization system. The results were satisfactory as we expected, and we have concluded that they can be used successfully as data in further processing such as segmentation or extraction of characters. Furthermore, the method helps to increase the eventual efficiency of a recognition system for poor-quality word images, such as number plate photos with non-uniform illumination and low contrast.

Goal-oriented analysis and use case analysis are well known requirements analysis methods and are putting into practice. Roughly speaking, goal-oriented methods are suitable for eliciting constraints to a system and use case analysis methods elicit concrete system behavior. Thus these methods are complementary and their integration into a new method allows us to get a more powerful requirements elicitation method. This paper proposes a new method where both of the methods are amalgamated. In our method, constraints to the system are refined by goal-oriented style, while system behavior are described with hierarchical use cases. Since a use case is made relate to goals during our elicitation processes, the decomposition of goals and use cases are complementally supported. Furthermore we applied our method to a couple of development projects and assessed its effectiveness.

This paper presents time slot assignment algorithms applicable to uplink of space division multiple access (SDMA)/time division multiple access (TDMA) systems with adaptive antennas. In the time slot assignment process for a new terminal in a cell, we consider not only the signal quality of the new terminal but also that of active terminals in the same cell. Intra-cell hand over is performed for an active terminal when its signal quality deteriorates. We evaluate the blocking and forced termination probabilities for pure TDMA systems, sectorized systems, and SDMA/TDMA systems in cellular environments by computer simulations. The simulation results show that the SDMA/TDMA systems have much better performance than the pure TDMA and sectorized systems.

This paper presents a novel algorithm which generates a beam pattern having maximum gain towards target direction. The new technique utilizes a Generalized Conjugate Gradient Method (CGM) based on the conventional CGM for obtaining the optimal weight vector. The proposed method finds a weight vector that maximizes the SINR (Signal to Interference plus Noise Ratio). Based on the an analysis of the results of various computer simulations, it is observed that the proposed algorithm is suitable for the IS2000 1X mobile communication environments.

This paper describes the design concept and implementation of a software platform for realization of symbiotic robots that interact intelligently with human in symbiosis manner. Such robots require proper combination of various technologies on a common platform that allows them to work co-operatively. "SPAK" has been developed to serve this purpose. It is a Java-based software platform to support knowledge processing and co-ordination of tasks among several software modules and agents representing the robotic hardware connected on a network. SPAK features frame-based knowledge system, a GUI knowledge building tool, forward and backward chaining engines, networking support, and class libraries for building software agent components. Beside the robotic applications, SPAK can be used as a general-purpose frame system as well. An experimental application of SPAK in human-robot interaction is also given.

Using event-related potential (P300 and CNV), the cognitive function of elderly subjects was compared with that of young subjects. It was found that the prolonged cognitive information processing induced by aging was reflected in the P300 and N400 latency. The effects of aging were not observed in the P300 amplitude. The CNV measurements, in the range of this study, did not reflect the effects of aging. This might be because the CNV reflects a higher cognitive function as compared with P300 and the effects of aging do not appear in such a function. The data also suggested that the cognitive style must be taken into account when evaluating the deterioration of cognitive functions with aging.

Normally, flow field is described with governing equations, such as the Navier-Stokes equations. However, for complex flow including multiphase and reactive flow such as combustion, this approach may not be suitable. As an alternative approach, Lattice Gas Automata (LGA) has been used to simulate fluid with mesoscopic particles by assuming that space and time are discrete, and the physical quantities take only a finite set of values. In this study, the model for combustion simulation is proposed, with the reaction probability depending on the local temperature to simplify the chemical reaction. Here, counter-flow twin flames are simulated. In order to validate this approach, some results of non-reactive flow are presented, compared with those by solving Navier-Stokes equations.

This paper proposes a new supply current test method for detecting floating gate defects in CMOS ICs. In the method, unusual increase of the supply current caused by defects is promoted by superposing an AC component on the DC power supply. Feasibility of the test is examined by some experiments on four DUTs with an intentionally caused defect. The results showed that our method could detect clearly all the defects, one of which may be detected by neither any functional logic test nor any conventional supply current test.

In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.

This paper describes a method of test data compression for a given test set using statistical encoding. In order to maximize the effectiveness of statistical encoding, the method first converts some specified input values in the test set to unspecified ones without losing fault coverage, and then reassigns appropriate logic values to the unspecified inputs. Experimental results for ISCAS-89 benchmark circuits show that the proposed method can on the average reduce the test data volume to less than 25% of that required for the original test set.

In this paper, we analyze behaviors of bridging faults in CMOS synchronous sequential circuits based on transient analysis. From analysis results, we expose dynamic and analog behaviors of the circuit caused by the bridging faults, which are oscillation, asynchronous sequential behavior, IDDT failure and IDDQ failure as well as logic error. In order to detect this kind of fault, we show that not only IDDQ testing but also IDDT testing and logic testing which guarantees correct state transitions are required.