In this paper, we investigate Tanner's lower bound for the minimum distance of regular LDPC codes based on combinatorial designs. We first determine Tanner's lower bound for LDPC codes which are defined by modifying bipartite graphs obtained from combinatorial designs known as Steiner systems. Then we show that Tanner's lower bound agrees with or exceeds conventional lower bounds including the BCH bound, and gives the true minimum distance for some EG-LDPC codes.

We describe 150-nm-thick collector InP-based double heterojunction bipolar transistors with two types of thin pseudomorphic bases. The emitter and collector layers are designed for high collector current operation. The collector current blocking is suppressed by the compositionally step-graded collector structure even at JC of over 500 kA/cm2 with practical breakdown characteristics. An HBT with a 20-nm-thick base achieves a high fT of 351 GHz at high JC of 667 kA/cm2, and a 30-nm-base HBT achieves a high value of 329 GHz for both fT and fmax at JC of 583 kA/cm2. An equivalent circuit analysis suggests that the extremely small carrier-transit-delay contributes to the ultrahigh fT.

In an optical time domain reflectometer type strain measurement system, we theoretically derive the shape of the Brillouin gain spectrum produced in an optical fiber under a parabolic strain distribution which is formed in a uniformly loaded beam. Based on the derived result, we investigate the effects of the parabolic strain distribution parameters and the measurement conditions such as the launched pulse width and the measurement position on the beam on the deformation of the Brillouin backscattered-light power spectrum shape. In addition, we investigate the strain measurement error resulting from the deformation of the power spectrum shape by analyzing the peak-power frequency at which the power spectrum is maximized.

We developed a SPARC-V9 processor, the SPARC64 V. It has an operating frequency of 1.35 GHz and contains 191 million transistors fabricated using 0.13-µm CMOS technology with eight-layer copper metallization. SPECjbb2000 (CPU# 32) is 492683, highest on the market and 42% higher than the next highest system. SPEC CPU2000 performance is 858 for SPECint and 1228 for SPECfp. The processor is designed to provide the high system performance and high reliability required of enterprise server systems. It is also designed to address the performance requirements of high-performance computing. During our development of several generations of mainframe processors, we conducted many related experiments, and obtained enterprise server system (EPS) development skills, an understanding of EPS workload characteristics, and technology that provides high reliability, availability, and serviceability. We used those as bases of the new processor development. The approach quite effectively moves beyond differences between mainframe and SPARC systems. At the beginning of development and before the start of hardware design, we developed a software performance simulator so we could understand the performance impacts of created specifications, thereby enabling us to make appropriate decisions about hardware design. We took this approach to solve performance problems before tape-out and avoid spending additional time on design update and physical machine reconstruction. We were successful, completing the high-performance processor development on schedule and in a short time. This paper describes the SPARC64 V microprocessor and performance analyses for development of its design.

In this paper we present an unsupervised color image segmentation algorithm based on statistical models. We have adopted the Gaussian mixture model to represent the distribution of color feature vectors. A novel deterministic annealing EM and mean field theory from statistical mechanics are used to compute the posterior probability distribution of each pixel and estimate the parameters of the Gaussian Mixture Model. We describe the noncontexture segmentation algorithm that uses a deterministic annealing approach and the contexture segmentation algorithm that uses the mean field theory. The experimental results show that the deterministic annealing EM and mean field theory provide a global optimal solution for the maximum likelihood estimators and that these algorithms can efficiently segment the real image.

We present excellent performance of a novel two-stage SiGe hetero-bipolar transistor (HBT) power amplifier (PA) in which different collector doping structures were employed for the first and second stages. A selectively ion implanted collector (SIC) structure was employed for the first stage HBT in order to obtain a high gain, while without-SIC structure was used for the second stage HBT in order to achieve a high breakdown voltage. At 1.95 GHz, the total PAE of 31% and a gain of 28 dB with an output power (Pout) of 26 dBm were obtained while the adjacent channel power ratio (ACPR) was less than -38 dBc for W-CDMA modulation signals.

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 µm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.

Suica is our contact-less IC card's nickname: Super Urban Intelligent CArd. There are two types of IC Card: One for Suica IO (SF) Card and the other for Suica Commuter Pass, which has a function of stored fare card and commuter pass. There are 6.54 million Suica holders (about 3.33 million Suica Season Pass holders and 3.21 million Suica IO Card holders) as of 16, June 2003.

An approach is proposed for constructing a dependable server cluster composed only of server nodes with all nodes running the same algorithm. The cluster propagates an IP multicast address as the server address, and clients multicast requests to the cluster. A local proxy running on each client machine enables conventional client software designed for unicasting to communicate with the cluster without having to be modified. Evaluation of a prototype system providing domain name service showed that a cluster using this technique has high dependability with acceptable performance degradation.

Detecting the possibility of inference attacks is necessary in order to keep a database secure. Inference attacks mean that a user tries to infer the result of an unauthorized queries to the user. For method schemas, which are a formal model of object-oriented databases, it is known that the security problem against inference attacks is decidable in polynomial time in the size of a given database instance. However, when the database instance or authorization has slightly been updated, it is not desirable to check the entire database again for efficiency. In this paper, we propose several sufficient conditions for update operations to preserve the security. Furthermore, we show that some of the proposed sufficient conditions can be decided much more efficiently than the entire security check. Thus, the sufficient conditions are useful for incremental security checking.

This paper describes the architecture of ReVolver/C40 a scalable parallel machine for volume rendering and its prototype implementation. The most important feature of ReVolver/C40 is view-independent real time rendering of translucent 3D object by using perspective projection. In order to realize this feature, the authors propose a parallel volume memory architecture based on the principal axis oriented sampling method and parallel treble volume memory. This paper also discusses the implementation issues of ReVolver/C40 where various kinds of parallelism extracted to achieve high-perfromance rendering are explained. The prototype systems had been developed and their performance evaluation results are explained. As the results of the evaluation of the prototype systems, ReVolver/C40 with 32 parallel volume memory is estimated to achieve more than 10 frame per second for 2563 volume data on 2562 screen by using perspective projection. The authors also review the development of ReVolver/C40 from several view points.

This study investigate the rectangular microstrip patch antenna on anisotropy substrates with superstrate and air gap, based on rigorous full-wave analysis and Galerkin's moment method. Results show that radiation patterns with varying air gap, permittivity of the superstrate and substrate, and thickness of the superstrate can be determined and analyzed.

High-frequency characterization and delay-time analysis have been performed for a short channel AlGaN/GaN heterojunction FET. The fabricated device with a short gate length (Lg) of 0.07 µm exhibited an extrinsic current gain cutoff frequency of 81 GHz and a maximum frequency of oscillation of 190 GHz with a maximum stable gain (MSG) of 8.2 dB at 60 GHz. A new scheme for the delay-time analysis was proposed, in which the effects of rather large series resistance RS + RD are properly taken into account. By applying the new scheme to a device with Lg=0.25 µm, we obtained an effective high-field electron velocity of 1.75107 cm/s, which is consistent with our previous results calculated using Monte Carlo simulation.

We present ultra low noise- and wide dynamic range performances of an AlGaN/GaN heterostructure FET (HFET). An HFET fabricated on a high quality epitaxial layers grown on a semi-insulating SiC substrate exhibited impressively low minimum noise figure (NF min ) of 0.4 dB with 16 dB associated gain at 2 GHz. The low NF (near NF min ) operation was possible in a wide drain bias voltage range, i.e. from 3 V to 15 V. At the same time, the device showed low distortion character as indicated by the high third order input intercept point (IIP3), +13 dBm. The excellent characteristics are attributed to three major factors: (1) high quality epitaxial layers that realized a high transconductance and very low buffer leakage current; (2) excellent device isolation made by selective thermal oxidation; (3) ultra low gate leakage current realized by Pd based gate. The results demonstrate that the AlGaN/GaN HFET is a strong candidate for front-end LNAs in various mobile communication systems where both the low noise and the wide dynamic range are required.

We have developed a novel self-alignment process using the surface tension of the liquid resin for assembly of electronic and optoelectronic devices. Due to their characteristics of low surface tension, however, the parametric design guidelines are necessary for resin self-alignment capability. In this paper, a shape prediction mathematical model and a numerical method are developed. The developed system is capable of achieving the liquid joint geometry and the parametric design for self-alignment capability. The influences of geometric parameters such as liquid volume, component weight, pad radius, liquid surface tension on the shape of liquid joint are investigated. Furthermore, the parametric design guidelines considered the process-related practical matters of misalignment level, distribution of the supplied liquid volumes and coplanarity deviation includes difference of the height between the pads are provided.

RF diamond FETs have been realized on a hydrogen-terminated diamond surface conductive layer. By utilizing the self-aligned gate fabrication process which is effective for the reduction of the parasitic resistance, the transconductance of diamond FETs has been greatly improved. Consequently, the high frequency operation of 22 GHz has been realized in 0.2 µ m gate diamond MISFETs with a CaF2 gate insulator. This value is the highest in diamond FETs and is comparable to the maximum value of SiC MESFETs at present.

We study the advantages and limitations of InP/GaAsSb/InP DHBTs for high-speed digital circuit applications. We show that the high-current performance limitation in these devices is electrostatic in nature. Comparison of the location of collector current blocking in various collector designs suggests a smoother, more gradual onset of blocking effects in type-II collectors. A comparison of collector current blocking effects between InP/GaAsSb--based and various designs of InP/GaInAs--based DHBTs provides support for our analysis.

A low energy plasma based on an electron discharge was investigated for the pre-epi clean of silicon wafers and for plasma enhanced homo and hetero epitaxial growth of Si and SiGe layers. VS were produced in a short, completely dry process sequence consisting of LEPC and LEPECVD only. The wafer/epilayer interface obtained in this process sequence was suitable to grow high quality VS with low surface roughness and dislocation densities. Based on this process and its implementation in a 200/300 mm single wafer cluster tool, a high volume and economical production of VS seems possible.

TCAD is gaining acceptance in the heterostructure industry. This article discusses the specific challenges a device simulator must manage to be a useful tool in designing and optimizing modern heterostructure devices. Example simulation results are given for HEMTs and HBTs, illustrating the complex physical processes in heterostructure devices, such as nonlocal effects in carrier transport, lattice self-heating, hot-electron effects, traps, electron tunneling, and quantum transport.

The DC resistivities of silicon germanium thin films on Si substrates by a non-contact and non-destructive technique using terahertz time domain spectroscopy (THz-TDS) agree with the values obtained by the four-point probe measurement. In the present experiment, the mobility has not been precisely determined owing to the limitation of the frequency range in our equipment (from 0.1 to 1.5 THz). However, when the mobility becomes large enough, this method will be highly useful in evaluating semiconductor thin films, since the method gives the same data as those from Hall measurement without sample processing or electrode contact to sample.