An extended desktop multimedia conference system named FREDERIC (File Retrieval Engineering on Distributed EnviRonment and Interactive Communication system) has been developed for international cooperative work by sharing CAD and image data among multi-point users. This paper describes the basic network design concept of utilizing the Internet as a best-effort service and ISDN as a high-speed guaranteed service. Service system requirements and designs were developed to access common databases and collaborative work of multimedia information those are shared by customers with desktop computers and to allow remote offices to use a plant walkthrough system. The performance of the prototype system especially focused on the file transmission time which is the key factor in developing and constructing the system. By applying the image compression technology of multi-tone entropy coding, it is shown that the short time CAD data transfer to meet the requirements can be achieved.

A major topic in the field of network and telecommunications is doing business on the World Wide Web (WWW), which is called Electronic Commerce (EC). Another major topic is blending Artificial Intelligence (AL) techniques with the WWW. In the Ex-W-Pert Project we have proposed an agent model for EC components that blends the traditional expert systems' reasoning engine with a multi-layer knowledge base, communication and documentation engines. In this project, EC is viewed as a society of software agents, such as customer, search, catalog, manufacturer, dealer, delivery and banker agents, interacting and negotiating with each other. Each agent has a knowledge-base and a reasoning engine, a communication engine and a documentation engine. The knowledge-base is organized in three layers: skill layer, rule layer and knowledge layer (S-R-K layers). In this project, for each EC agent, we identify the class of problems to be solved and build the knowledge base gradually for each layer. We believe that using this multi-layer knowledge base system will speed up the reasoning and ultimately reduce the operation costs.

The productivity of developing software for switching systems and the effects of using advanced software development methods were evaluated and analyzed. Productivity was found to be improved by using automatic code generation, simulator debugging, a hierarchical object-oriented software structure, and software-development-support tools. The evaluation showed that the total productivity was improved by about 20%, compared with a case where these efforts were not introduced. It also showed each effect of these methods and tools by evaluating their manpower saving ratios. These results are expected to benefit the development of various types of communication-switching and multimedia service systems. Also, our development-support tools and methods are expected to be the basis for attaining higher software development productivity.

This paper presents a timing-driven global routing algorithm based on coarse pin assignment, block reshaping, and positioning for VLSI building block layout. As opposed to conventional approaches, we combine pin assignment and global routing problems into one problem. The proposed algorithm determines global routes, coarse pin assignments, and block shapes and positions so as to minimize the chip area and total wire length of nets under the given timing constraints. It is based on an iterative improvement paradigm and performs rip-up and rerouting, block reshaping, and positioning in the manner of simulated evolution taking shapes of soft blocks and routing congestion into consideration until the solution is not further improved. The Elmore delay model is adopted for the interconnection delay model. Experimental results show the effectiveness of the proposed algorithm.

This paper presents a new binding algorithm for a retargetable compiler which can deal with diverse architectures of application specific embedded processors. The architectural diversity includes a "non-orthogonal" datapath configuration where all the registers are not equally accessible by all the functional units. Under this assumption, binding becomes a hard task because inadvertent assignment of an operation to a functional unit may rule out possible assignment of other operations due to unreachability among datapath resources. We propose a new BDD-based algorithm to solve this problem. While most of the conventional methods are based on the covering of expression trees obtained by decomposing DFGs, our algorithm works directly on the DFGs so as to avoid infeasible bindings. In the experiments, a feasible binding which satisfies the reachability is found or the deficiency of datapath is detected within a few seconds.

In this paper we have introduced a new method for signature pattern recognition, taking advantage of some image moment transformations combined with fuzzy logic approach. For this purpose first we tried to model the noise embedded in signature patterns inherently and separate it from environmental effects. Based on the first step results, we have performed a mapping into the unit circle using the error least mean square (LMS) error criterion, to get ride of the variations caused by shifting or scaling. Then we derived some orientation invariant moments introduced in former reports and studied their statistical properties in our special input space. Later we defined a fuzzy complex space and also a fuzzy complex similarity measure in this space and constructed a new training algorithm based on fuzzy learning vector quantization (FLVQ) method. A comparison method has also been proposed so that any input pattern could be compared to the learned prototypes through the pre-defined fuzzy similarity measure. Each set of the above image moments were used by the fuzzy classifier separately and the mis-classifications were detected as a measure of error magnitude. The efficiency of the proposed FLVQ model has been numerically shown compared to the conventional FLVQs reported so far. Finally some satisfactory results are derived and also a comparison is made between the above considered image transformations.

We have analyzed a very short channel tunneling field effect transistor which uses new heterostructures (CoSi2/Si/CdF2/CaF2) lattice-matched to the Si substrate. In device operation, the drain current from source (CoSi2) to drain (CoSi2) through tunnel barriers (Si) and the channel (CdF2) is controlled by a gate electric field applied to the barrier between the source and the channel through the gate insulator (CaF2). Theoretical analysis shows that this transistor has characteristics similar to those of conventional metal-oxide-semiconductor field effect transistors even with channel lengths as short as 5 nm. In addition, we have estimated the theoretical response time of this transistor and showed the possibility of subpicosecond response.

Page-based DSM systems suffer from false sharing since they use a large page as a coherence unit. The optimal page size is dynamically affected by application characteristics. Therefore, a fixed-size page cannot satisfy various applications even if it is small as a cache line size. In this paper we present a software-only coherence protocol called BCP (Buddy Coherence Protocol) to support multiple page sizes that vary adaptively according to the behavior of each application during run time. In BCP, the address of a remote access and the address of the most recent local access is compared. If they are to the different halves of a page, BCP considers it as false sharing and demotes the page to two subpages of equal size. If two contiguous pages belong to the same node, BCP promotes two pages to a superpage to reduce the number of the following coherence activities. We also suggest a mechanism to detect data sharing patterns to optimize the protocol. It detects and keeps the sharing pattern for each page by a state transition mechanism. By referring to those patterns, BCP selectively demotes the page and increases the effectiveness of a demotion. Self-invalidation of the migratorily shared page is also employed to reduce the number of invalidations. Our simulations show that the optimized BCP outperforms almost all the best cases of the write-invalidate protocols using fixed-size pages. BCP improves performance by 42.2% for some applications when compared against the case of the fixed-size page.

The influence of loaded capacitance on the resonant frequency of a triplate-type strip resonator is investigated through numerical simulations by means of the finite-difference time-domain (FDTD) method. This type of resonator is one of the basic components of very small high-dielectric stripline filters, named laminated planar filters. Numerical results of resonant frequencies are compared with experimental results and found to be in excellent agreement, which circumstance ensures that the FDTD method can be applied to the characterization of a wide range of laminated planar microwave devices including resonators and filters. It is also found that the resonant frequency is directly related to the square root of its line capacitance when the resonator is regarded equivalently as a series LC circuit.

The objective of thinning is to reduce the amount of information in image patterns to the minimum needed for recognition. Thinned image helps the extraction of important features such as end points, junction points, and connections from image patterns. The ultimate goal of parallel algorithms is to minimize the execution time while producing high quality thinned image. Though much research has been performed for parallel thinning algorithms, there has been no systematical approach for comparing the execution speed of parallel thinning algorithms. Several rough comparisons have been done in terms of iteration numbers. But, such comparisons may lead to wrong guides since the time required for iterations varies from one algorithm to the other algorithm. This paper proposes a formal method to analyze the performance of parallel thinning algorithms based on PRAM (Parallel Random Access Machine) model. Besides, the quality of skeletons, robustness to boundary noise sensitivity, and execution speed are considered. Six parallel algorithms, which shows relatively high performance, are selected, and analyzed based on the proposed analysis method. Experiments show that the proposed analysis method is sufficiently accurate to evaluate the performance of parallel thinning algorithms.

In this paper, we represent a class structure using directed graph in which each node corresponds to each member of the class. To quantify the dependence relationship among members, we define weighted closure. Using this quantified relationship and effort equation proposed by M. H. Halstead, we propose a metric for class structural complexity.

Excitation of magnetostatic surface waves by coplanar waveguide transducers is analyzed by using the integral kernel expansion method. The Fourier integral for the current density is derived in terms of an unknown normal component of the magnetic flux density on slot region of a coplanar waveguide. The integral kernel is expanded into a series of Legendre polynomials and then applying Galerkin's method to the unknown field reduces the Fourier integral to a system of linear equations for the unknown coefficients. In this process, we should take into account the edge conditions which show nonreciprocal characteristics depending on frequency. The present method shows excellent agreement with experiments.

A method is proposed for deriving a traffic characteristics model that can be used to forecast the traffic volume for intelligent telecommunication services. A sort of regression analysis with dummy variables is used to represent the service quantitatively and to construct the traffic characteristics model. Recursive least squares estimation, which is a special case of the Kalman filter, is applied to the traffic characteristics model to forecast the traffic volume. In the proposed modeling and forecasting, qualitative factors representing a certain service attribute are selected and using an information criterion, the model with the best fit is identified as the most suitable forecasting model. Numerical results using practical observation data showed that the proposed method produces an accurate forecast and is thus effective for practical use.

Analysis of frequency-dependent lossy transmission lines is very important for designing the high-speed VLSI, MCM and PCB. The frequency-dependent parameters are always obtained as tabulated data. In this paper, a new curve fitting technique of the tabulated data for the moment matching technique in the interconnect analysis is presented. This method based on Chebyshev interpolation enhances the efficiency of the moment matching technique.

The importance of technology retargeting for hard IPs is getting increased. However, recent advances in process technologies make layout reuse too complicated to be done by conventional compactors. As an efficient approach, this paper proposes a flexible layout abstraction model and a new layout synthesis algorithm. The synthesis algorithm provides a concurrent procedure of detailed wiring, compaction, and transistor layout generation by using a scan line to get better layout results than conventional compactors. We have applied this method to the technology retargeting of actual cell layouts and have achieved quite good results comparable to hand-crafted designs.

The mapping from a global routing to a feasible detailed routing in a number of 2D array routing structures has been shown to be an NP-complete problem. These routing structures include the Xilinx style routing architecture, as well as architectures with significantly higher switching flexibility. In response to this complexity, a different class of FPGA routing structures called Greedy Routing Architectures (GRAs) have been proposed. On GRAs, optimally routing each switch box, in a specified order, leads to an optimal chip routing. Because routing each switch box takes polynomial time, the mapping problem on GRAs can be solved in polynomial time. In particular, an H-tree GRA with W2+2W switches per switch box (SpSB) and a 2D array GRA with 4W2+2W SpSB have been proposed. In this paper, we improve on these results by introducing an H-tree GRA with W2/2+2W SpSB and a 2D array GRA with 3.5W2+2W SpSB. These new GRAs have the same desirable mapping properties of the previously described GRAs, but use fewer switches.

This paper reports on an Intelligent CASE tool, applicable in a structured programming phase, or from detailed design to coding. This is automation of the bottom level in the hierarchical design process of detailed design and coding, where the largest man-hours are consumed. The main idea is that human designers use a CASE tool for the initial design of a software system, and the design knowledge is automatically acquired from the structured charts and stored in the knowledge base. The acquired design knowledge may be reused in designs. By reusing it, a similar software system may be designed automatically. It has been shown that knowledge acquired in this way has a Logarithmic Learning Effect. Based on this, a quantitative evaluation of productivity is made. By accumulating design experiences (e. g. 10 times), more than 80% of the detailing designs are performed automatically, and productivity increases by up to 4 times. This tool features universality, an essentially zero start-up cost for automatic design, and a substantial increase in software productivity after enough experiences have been accumulated. This paper proposes a new basic idea and its implementation, a quantitative evaluation applying techniques from Industrial Engineering, which proves the effectiveness of the proposed system.

This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

A fuel cell energy system is under development for supply of generated electrical energy to telecommunications equipment. It is a cogeneration system; the heat energy recovered is used to cool the telecommunications equipment. For this system, a method is described for controlling a new DC interconnection converter. Its DC interconnection characteristics are also discussed. The new converter controls its input current to the fuel cell rated current at maximum and can operate stably even when the fuel cell voltage decreases. This allows good DC interconnection characteristics to be obtained in both the steady state and the transient state.

The datapath width of a core processor has a strong effect on cost, power consumption, and performance of an embedded system integrated with memories into a single-chip. However, it is difficult for designers to appropriately determine the datapath width for each application because of the limited reusability of software and the lack of compilation techniques. The purpose of this paper is to clarify supports required from software for the optimal datapath width determination. As a solution, an embedded programming language, called Valen-C, and a retargetable Valen-C compiler are proposed. In this paper, the syntax and semantics of Valen-C along with the mechanism of the Valen-C retargetable compiler and how to preserve the accuracy of computation of programs in relation to various datapath widths are also described. Experiments with practical applications show that the total cost of the system including a core processor, ROM, and RAM is drastically reduced with little performance loss by reducing the datapath width.