The Conjugate Residual method, one of the iterative methods for solving linear systems, is applied to the problems with a dense coefficient matrix on distributed memory parallel computers. Based on an assumption on the computation and communication times of the proposed algorithm for parallel computers, it is shown that the optimal number of processing elements is proportional to the problem size N. The validity of the prediction is confirmed through numerical experiments on Hitachi SR2201.

The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.

Three types of mechanisms were evaluated to determine their applicability to partially modifying an online switching system file and to creating a partial file during the debugging phase. First, the applicability of the basic plug-in mechanism, currently used in commercial switching systems, was evaluated by using data obtained from an initial implementation of PHS and ATM switching systems. It was found to be applicable irrespective of software type (call-processing or OA&M) and service type (PHS or ATM). It was also found to be applicable to both specification changes and service feature additions. Then, an extended plug-in mechanism that is enhanced to be more robust against complicated software behaviour was evaluated by simulation. It was found to cover cases where the basic plug-in mechanism is difficult to apply. Used together, these two mechanisms guarantee stable and effective file management of an online switching system. A plug-in for offline file creation was found to be applicable to almost all types of file modifications, except when the interface definition is significantly changed. These plug-in mechanisms can serve as the basis for managing the files in multimedia communication service systems.

Image processing about the vehicle is considered in this paper. When a vehicle is in a factory, image processing is applied for design and inspection, and when vehicle is on the road image processing is useful for Intelligent Transport Systems, which recently have been developed widely. There have been many researches and implementations using image sensors to get information for traffic control and vehicle control. The image seen from camera located beside or upon the road can be used for vehicle detection, velocity of car or car group measurement, parking car detection, etc. Moreover the image seen from camera located in vehicle can be used for preceding car detection, measurement of the distance to preceding car, obstacle detection, lane detection, etc. In this paper, studies about Image Processing for vehicle on the road are described.

We fabricated and evaluated a second-order ΣΔ ADC with a polarity alternating feedback (PAF) comparator based on 0.4 µm InGaP/InGaAs enhancement and depletion mode high electron mobility transistors (E/D HEMT) technology. We propose a PAF technique for enhancing the sampling frequency and have applied the technique in the design of ADC circuit. The ADC has a signal-to-noise ratio (SNR) of 43 dB when operating at a differential clock frequency of 4.9 GHz, and has a power dissipation of 400 mW.

This paper is consisting of the two novel EMC technologies that we have been developed in our laboratory. The first is the technology for measuring the RF (Radio Frequency) nearby magnetic field and estimation of the RF current in the printed circuit board (PCB) by using the small loop antenna with multi-layer PCB structure developed by our laboratory. I introduce the application of our small loop antenna with its physical structure and the analysis of the nearby magnetic field distribution of the printed circuit board applying the discrete Wavelet analysis. We can understand the behavior of the digital circuit in detail, and we can also take measures to meet the specification about the electromagnetic radiation from the digital circuit from the higher order of priority by using these technologies. The second is our proposing novel technology for reducing the electromagnetic radiation from the digital equipment by taking notice of the improvement of the de-coupling in the PCB. We confirmed the remarkable effect of this technology by redesigning the motherboard of the small-sized computer.

This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.

A high-speed static logic circuit, the 1:8 demultiplexer (DEMUX), fabricated using single-gate CMOS technology (single-gate means the structure consisting of n+ poly-Si gate for both NMOS and PMOS transistors) has been demonstrated. To suppress short-channel effects in PMOS transistors, we only used the low-energy ion implantation (I/I) of BF2 at 10 keV for counterdoping of the channel and that at 5 keV for source/drain (S/D) extension. To control the threshold voltage Vth of PMOS transistors precisely, the channel dopants were implanted after the growth of the gate oxide because of the suppression of the transient-enhanced diffusion (TED) of boron, and the suppression of boron out-diffusion. A tree-type 1:8 DEMUX circuit composed of 0. 134 µm gate CMOS transistors operates at a high speed of 3.1 GHz and consumes a low power of 35.5 mW/GHz at VDD = 2.0 V. In this single-gate CMOS circuit, down to this small gate length, the maximum operating frequency of the DEMUX circuit increases proportionally with an increase of the inverse of the gate length without an increase of power consumption per GHz. At a practical 2.48832 Gb/s operation, the power consumption was 88 mW, and the phase margin between the input clock signal and the input data signal was 260 ps. It is suggested that a circuit composed of a single-gate CMOS transistor with 0.15 µm gate generation can be applicable to high speed ICs.

This report describes AlGaAs/GaAs HBT ICs for 20-Gb/s optical transmission, the preamplifier and optical modulator driver circuits, and those ICs for 10-Gb/s clock extraction circuits, the rectifier and phase shifter circuits. These ICs were fabricated using our developed hetero guard-ring fully self-aligned HBT (HG-FST) fabrication process. The Pt-Ti-Pt-Au multimetal system was also used as a base ohmic metal to reduce base contact resistance, and a high fmax of 105 GHz was obtained. Good results in the HBT IC microwave performances were achieved from the on-wafer measurements. The preamplifiers exhibited the broad bandwidth of 20. 9 GHz. The optical modulator driver performed a sufficiently large output-voltage swing of 4-VP-P at a 20-Gb/s data rate. The rectifier and the phase shifter circuits achieved good operations at 10-Gb/s. These results suggest that these HBT ICs can be applied to 20-Gb/s optical transmission and 10-Gb/s clock extraction systems.

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.

We have developed a fabrication technique for high-performance high-thermal-stability InP/InGaAs heterojunction bipolar transistors (HBTs) for use in 40-Gb/s ICs. The HBT's T-shaped emitter electrode structure simplifies the fabrication process and enables high controllability of spacing between the emitter and the base electrodes. A highly-C-doped base, grown by gas-source MBE, and a new Pt-based metal system results in a low base resistance. An InP subcollector suppresses thermal runaway of HBTs at high collector current better than a conventional InGaAs subcollector does. Using these techniques, we fabricated a very-high-performance HBT with an extremely high cutoff frequency fT of 235 GHz. The RF measurements show that the collector current at the peak cutoff frequency is inversely proportional to collector thickness. We also fabricated a static 1/2 frequency divider, that can be used for 40-Gb/s optical transmission systems, operating up to 44 GHz. This divider confirmed that the developed HBT is applicable to 40-Gb/s optical transmission ICs.

Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (VDD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cgsint) and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.

In this paper, we propose a method to detect a road sign from a road scene image in the daytime. In order to utilize color feature of sign efficiently, color distribution of sign is examined, and then color similarity map is constructed. Additionally, color similarity shown on the map is incorporated into image energy of an active net model. A road sign is extracted as if it is wrapped up in an active net. Some experimental results obtained by applying an active net to images are presented.

Optical frontend and distributed amplifier IC modules, both containing GaAs heterojunction-bipolar-transistors (HBT), have been developed for 40 Gb/s optical receiver. To achieve high-speed operations, the elements in the modules including the IC and signal lines, were designed to achieve a wider bandwidth with lower electrical reflection. The influence of a bonding-wire inductance was taken into particular account in optimizing the parameters of the ICs. The optical frontend, consisting of a waveguide pin-photodiode and an HBT preamplifier IC, exhibits a transimpedance gain of 43 dBΩ and a bandwidth of 31 GHz. The distributed amplifier IC module achieves a gain of 9 dB and a bandwidth of 39 GHz. A 40-Gb/s optical receiver constructed with these modules exhibited a high receiver sensitivity of -28. 2 dBm for a 40-Gb/s optical return-to-zero signal.

Phase performance in a fiber optic temperature sensor using a mode-division multiplex is studied. The phase shift due to the temperature change of a multimode graded-index optical fiber is analyzed. The intensity fluctuation by the interference of two modes is estimated in computer simulation.

This paper describes a flip-flop circuit using a directly controlled emitter-follower with a diode-feedback level stabilizer (DC-DF) and a resistor-feedback level stabilizer (DC-RF) for low-power multi-GHz prescalers. The new flip-flop circuit reduces the emitter-follower current and gains both high-frequency operation and low-power. A dual modulus (4/5) prescaler using this circuit technology was fabricated with a 0.35 µm BiCMOS process. The current draw of the prescaler using the DC-RF is 34% smaller than conventional LCML circuits. The DC-RF prescaler operates at 2.11 GHz with a total current consumption of 1.03 mA. In addition, the circuit operates with a supply voltage of down to 2.4 V by using the resistor level-shift clock-driver.

In Adleman's Function Field Sieve algorithm solving the discrete logarithm problem in a finite field, it is assumed that a random bivariate polynomial in the certain class is absolutely irreducible with high probability. In this letter we point out that if we use Cab type random polynomials then we always get absolutely irreducible polynomials. We can also simplify the calculation of a product of many rational functions on a curve that belongs to the field of definition by the use of a Cab curve.

In this paper, the generalized learning vector quantization (GLVQ) algorithm is applied to design a hand-written Chinese character recognition system. The system proposed herein consists of two modules, feature transformation and recognizer. The feature transformation module is designed to extract discriminative features to enhance the recognition performance. The initial feature transformation matrix is obtained by using Fisher's linear discriminant (FLD) function. A template matching with minimum distance criterion recognizer is used and each character is represented by one reference template. These reference templates and the elements of the feature transformation matrix are trained by using the generalized learning vector quantization algorithm. In the experiments, 540100 (5401 100) hand-written Chinese character samples are used to build the recognition system and the other 540100 (5401 100) samples are used to do the open test. A good performance of 92.18 % accuracy is achieved by proposed system.

The goal of this paper is to present a critical survey of existing literature on an omnidirectional sensing. The area of vision application such as autonomous robot navigation, telepresence and virtual reality is expanding by use of a camera with a wide angle of view. In particular, a real-time omnidirectional camera with a single center of projection is suitable for analyzing and monitoring, because we can easily generate any desired image projected on any designated image plane, such as a pure perspective image or a panoramic image, from the omnidirectional input image. In this paper, I review designs and principles of existing omnidirectional cameras, which can acquire an omnidirectional (360 degrees) field of view, and their applications in fields of autonomous robot navigation, telepresence, remote surveillance and virtual reality.

Optimum filters for an image restoration are formed by a degradation operator, a covariance operator of original images, and one of noise. However, in a practical image restoration problem, the degradation operator and the covariance operators are estimated on the basis of empirical knowledge. Thus, it appears that they differ from the true ones. When we restore a degraded image by an optimum filter belonging to the family of Projection Filters and Parametric Projection Filters, it is shown that small deviations in the degradation operator and the covariance matrix can cause a large deviation in a restored image. In this paper, we propose new optimum filters based on the regularization method called the family of Regularized Projection Filters, and show that they are stable to deviations in operators. Moreover, some numerical examples follow to confirm that our description is valid.