The Conjugate Residual method, one of the iterative methods for solving linear systems, is applied to the problems with a dense coefficient matrix on distributed memory parallel computers. Based on an assumption on the computation and communication times of the proposed algorithm for parallel computers, it is shown that the optimal number of processing elements is proportional to the problem size N. The validity of the prediction is confirmed through numerical experiments on Hitachi SR2201.

Recently, we proposed a low power consumption FIR switched-capacitor filter constructed with capacitors having capacitances in proportion to square roots of transfer function coefficient values. It is referred to as an FIR semi-parallel cyclic type (SPCT) filter. In this paper, we present IIR SPCT filter. It needs only a single operational amplifier, hence being low power consumption. The IIR SPCT filter has smaller total capacitance than one of the IIR parallel cyclic type (PCT) filter and better high frequency response than one of the IIR transfer function coefficient ratio (TCR) filter. As a whole, the IIR SPCT filter has middle performance of the IIR PCT and TCR filters for the total capacitance, the number of types of clock pulses, and high frequency response.

This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.

In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are reset, and the phase of the PLL frequency synthesizer is initialized and the phase synchronization is achieved. In the proposed method, since the ringing in the transient state does not occur, the output of the PLL frequency synthesizer converges to the target frequency at Ta and the frequency switching time is speeded up. The effectiveness of the proposed method will be confirmed by experimental results.

Three types of mechanisms were evaluated to determine their applicability to partially modifying an online switching system file and to creating a partial file during the debugging phase. First, the applicability of the basic plug-in mechanism, currently used in commercial switching systems, was evaluated by using data obtained from an initial implementation of PHS and ATM switching systems. It was found to be applicable irrespective of software type (call-processing or OA&M) and service type (PHS or ATM). It was also found to be applicable to both specification changes and service feature additions. Then, an extended plug-in mechanism that is enhanced to be more robust against complicated software behaviour was evaluated by simulation. It was found to cover cases where the basic plug-in mechanism is difficult to apply. Used together, these two mechanisms guarantee stable and effective file management of an online switching system. A plug-in for offline file creation was found to be applicable to almost all types of file modifications, except when the interface definition is significantly changed. These plug-in mechanisms can serve as the basis for managing the files in multimedia communication service systems.

Optical frontend and distributed amplifier IC modules, both containing GaAs heterojunction-bipolar-transistors (HBT), have been developed for 40 Gb/s optical receiver. To achieve high-speed operations, the elements in the modules including the IC and signal lines, were designed to achieve a wider bandwidth with lower electrical reflection. The influence of a bonding-wire inductance was taken into particular account in optimizing the parameters of the ICs. The optical frontend, consisting of a waveguide pin-photodiode and an HBT preamplifier IC, exhibits a transimpedance gain of 43 dBΩ and a bandwidth of 31 GHz. The distributed amplifier IC module achieves a gain of 9 dB and a bandwidth of 39 GHz. A 40-Gb/s optical receiver constructed with these modules exhibited a high receiver sensitivity of -28. 2 dBm for a 40-Gb/s optical return-to-zero signal.

Image processing about the vehicle is considered in this paper. When a vehicle is in a factory, image processing is applied for design and inspection, and when vehicle is on the road image processing is useful for Intelligent Transport Systems, which recently have been developed widely. There have been many researches and implementations using image sensors to get information for traffic control and vehicle control. The image seen from camera located beside or upon the road can be used for vehicle detection, velocity of car or car group measurement, parking car detection, etc. Moreover the image seen from camera located in vehicle can be used for preceding car detection, measurement of the distance to preceding car, obstacle detection, lane detection, etc. In this paper, studies about Image Processing for vehicle on the road are described.

In this paper, the generalized learning vector quantization (GLVQ) algorithm is applied to design a hand-written Chinese character recognition system. The system proposed herein consists of two modules, feature transformation and recognizer. The feature transformation module is designed to extract discriminative features to enhance the recognition performance. The initial feature transformation matrix is obtained by using Fisher's linear discriminant (FLD) function. A template matching with minimum distance criterion recognizer is used and each character is represented by one reference template. These reference templates and the elements of the feature transformation matrix are trained by using the generalized learning vector quantization algorithm. In the experiments, 540100 (5401 100) hand-written Chinese character samples are used to build the recognition system and the other 540100 (5401 100) samples are used to do the open test. A good performance of 92.18 % accuracy is achieved by proposed system.

Acquisition of three-dimensional information of a real-world scene from two-dimensional images has been one of the most important issues in computer vision and image understanding in the last two decades. Noncontact range acquisition techniques can be essentially classified into two classes: Passive and active. This paper concentrates on passive depth extraction techniques which have the advantage that 3-D information can be obtained without affecting the scene. Passive range sensing techniques are often referred to as shape-from-x, where x is one of visual cues such as shading, texture, contour, focus, stereo, and motion. These techniques produce 2.5-D representations of visible surfaces. This survey discusses aspects of this research field and reviews some recent advances including video-rate range imaging sensors as well as emerging themes and applications.

A novel method for the radiated immunity test is proposed. The method is to generate controlled electromagnetic fields applying in arbitrary directions to an under test. The fields rotate at a low speed controlled electrically so that the immunity characteristics may be known in more detail. The primal characteristics of the fields generated by a trial benchtop setup are investigated.

It is confirmed by simulation that SOI-DRAMs can be operated at high speed by using the floating body structures. Several floating body effects are analyzed. It is described that the dynamic retention characteristics are not dominated by capacitive coupling and hole redistribution. And it is described that those characteristics are determined by the leakage current in the small pn-junction region of the floating body. Reducing pn junction leakage current is important for realizing a long retention time. If the pn junction leakage is suppressed to 10-18 A/µm, a dynamic retention time of 520 sec at a VBSG of 0.5 V can be achieved at 27. On those conditions, the refresh current of SOI-DRAMs is reduced by 54% compared with bulk-Si DRAMs.

This paper describes a flip-flop circuit using a directly controlled emitter-follower with a diode-feedback level stabilizer (DC-DF) and a resistor-feedback level stabilizer (DC-RF) for low-power multi-GHz prescalers. The new flip-flop circuit reduces the emitter-follower current and gains both high-frequency operation and low-power. A dual modulus (4/5) prescaler using this circuit technology was fabricated with a 0.35 µm BiCMOS process. The current draw of the prescaler using the DC-RF is 34% smaller than conventional LCML circuits. The DC-RF prescaler operates at 2.11 GHz with a total current consumption of 1.03 mA. In addition, the circuit operates with a supply voltage of down to 2.4 V by using the resistor level-shift clock-driver.

In this paper, we consider the steady state mean square error (MSE) analysis for 2-D LMS adaptive filtering algorithm in which the filter's weights are updated along both vertical and horizontal directions as a doubly-indexed dynamical system. The MSE analysis is conducted using the well-known independence assumption. First we show that computation of the weight-error covariance matrix for doubly-indexed 2-D LMS algorithm requires an approximation for the weight-error correlation coefficients at large spatial lags. Then we propose a method to solve this problem. Further discussion is carried out for the special case when the input signal is white Gaussian. It is shown that the convergence in the MSE sense occurs for step size range that is significantly smaller than the one necessary for the convergence of the mean. Simulation experiments are presented to support the obtained analytical results.

Fluctuation characteristics of character centroid intervals in laterally written Japanese sentences are investigated by means of their spatial frequency characteristics. Power spectra of character centroid intervals in their longitudinal and transverse directions are obtained for handwritten and word processor printed sample sentences. It is shown that for fluctuation characteristics in the longitudinal direction, power spectra are inversely proportional to their spatial frequencies for handwritten sentences and proportional to them for word processor printed sentences, and there exists a remarkable difference between handwritten and word processor printed sentences. It is also shown that for fluctuation characteristics in the transverse direction, power spectra are proportional to their spatial frequencies for both handwritten and word processor printed sentences, and there is no remarkable difference between handwritten and word processor printed sentences.

A high-speed static logic circuit, the 1:8 demultiplexer (DEMUX), fabricated using single-gate CMOS technology (single-gate means the structure consisting of n+ poly-Si gate for both NMOS and PMOS transistors) has been demonstrated. To suppress short-channel effects in PMOS transistors, we only used the low-energy ion implantation (I/I) of BF2 at 10 keV for counterdoping of the channel and that at 5 keV for source/drain (S/D) extension. To control the threshold voltage Vth of PMOS transistors precisely, the channel dopants were implanted after the growth of the gate oxide because of the suppression of the transient-enhanced diffusion (TED) of boron, and the suppression of boron out-diffusion. A tree-type 1:8 DEMUX circuit composed of 0. 134 µm gate CMOS transistors operates at a high speed of 3.1 GHz and consumes a low power of 35.5 mW/GHz at VDD = 2.0 V. In this single-gate CMOS circuit, down to this small gate length, the maximum operating frequency of the DEMUX circuit increases proportionally with an increase of the inverse of the gate length without an increase of power consumption per GHz. At a practical 2.48832 Gb/s operation, the power consumption was 88 mW, and the phase margin between the input clock signal and the input data signal was 260 ps. It is suggested that a circuit composed of a single-gate CMOS transistor with 0.15 µm gate generation can be applicable to high speed ICs.

In Adleman's Function Field Sieve algorithm solving the discrete logarithm problem in a finite field, it is assumed that a random bivariate polynomial in the certain class is absolutely irreducible with high probability. In this letter we point out that if we use Cab type random polynomials then we always get absolutely irreducible polynomials. We can also simplify the calculation of a product of many rational functions on a curve that belongs to the field of definition by the use of a Cab curve.

This paper is consisting of the two novel EMC technologies that we have been developed in our laboratory. The first is the technology for measuring the RF (Radio Frequency) nearby magnetic field and estimation of the RF current in the printed circuit board (PCB) by using the small loop antenna with multi-layer PCB structure developed by our laboratory. I introduce the application of our small loop antenna with its physical structure and the analysis of the nearby magnetic field distribution of the printed circuit board applying the discrete Wavelet analysis. We can understand the behavior of the digital circuit in detail, and we can also take measures to meet the specification about the electromagnetic radiation from the digital circuit from the higher order of priority by using these technologies. The second is our proposing novel technology for reducing the electromagnetic radiation from the digital equipment by taking notice of the improvement of the de-coupling in the PCB. We confirmed the remarkable effect of this technology by redesigning the motherboard of the small-sized computer.

This paper proposes an algorithm for analyzing the reachability property of Petri nets by the use of unfoldings. It is known that analyzing the reachability by using unfoldings requires exponential time and space to the size of unfolding. The algorithm is based on the branch and bound technique, and experimental results show efficiency of the algorithm.

This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.