As wireless communication is penetrating every corner of the globe, the optimum design and accurate analysis of RF, power semiconductor devices become one of the biggest challenges in EDA and TCAD (Technology CAD) tool development. The performance gauge for these devices is quite different from that for either digital or analog devices aimed at small-signal applications in that the power gain, efficiency, and distortion (or the range of linearity) are the utmost design concerns. In this article, the methodology and mathematical foundation for numerical analysis of large signal distortion at the device simulation level are discussed. Although the harmonic balance (HB) method has long been used in circuit simulation for large signal distortion analysis, the implementation of the same method in device simulation faces daunting challenges, among which are the tremendous computational cost and memory storage management. But the benefits from conducting such a device level simulation are also obvious--for the first time, the impact of technology and structural variation of device on large signal performance can directly be assessed. The necessary steps to make the HB analysis feasible in device simulation are outlined and algorithmic improvement to ease the computation/storage burden is discussed. The applications of the device simulator for various RF power devices, including GaAs MESFETs and silicon LDMOS (lateral diffusion MOS) are presented, and the insight gained from such an analysis is provided.

In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

A device simulator that simulates device performance in the cyclic bias steady state was developed, and it was applied to GaAs hetero-junction FET (HJFET) pulse pattern effect. Although there is a large time-constant difference between the pulse signals and deep trap reactions, the simulator searches the cyclic bias steady states at about 30 iterations. A non-linear shift in the drain current level with the mark ratio was confirmed, which has been estimated from the rate equation of electron capture and emission based on Shockley-Read-Hall statistics for deep traps.

The full-band Monte Carlo technique is currently the most accurate device simulation method, but its usefulness is limited because it is very CPU intensive. This work describes efficient algorithms in detail, which raise the efficiency of the full-band Monte Carlo method to a level where it becomes applicable in the device design process beyond exemplary simulations. The k-space is discretized with a nonuniform tetrahedral grid, which minimizes the discretization error of the linear energy interpolation and memory requirements. A consistent discretization of the inverse mass tensor is utilized to formulate efficient transport parameter estimators. Particle scattering is modeled in such a way that a very fast rejection technique can be used for the generation of the final state eliminating the main cause of the inefficiency of full-band Monte Carlo simulations. The developed full-band Monte Carlo simulator is highly efficient. For example, in conjunction with the nonself-consistent simulation technique CPU times of a few CPU minutes per bias point are achieved for substrate current calculations. Self-consistent calculations of the drain current of a 60nm-NMOSFET take about a few CPU hours demonstrating the feasibility of full-band Monte Carlo simulations.

The full liquid crystal display (LCD) simulation with real transistors and other active components is unrealistic. Because a flat panel display (FPD) includes thin-film-transistors (TFT's) whose number is, at least, the number of total pixels. It hits the simulation limit of SPICE if the number of transistors are more than 0.5 million. This paper demonstrates a new, fast, and effective simulation method for a full LCD panel. The method makes it possible to simulate large LCD panels whereas the conventional method cannot handle. The simulation circuit consists of a-Si TFT model presented earlier, the liquid crystal, the pixel macro models, and interconnects. We show the model parameter extraction and the pixel macro modeling process associated with the simulation results. Using the simulation method presented here some larger LCD panels can be accurately simulated in less than a minute on a workstation.

Equipment simulation can provide valuable support in reactor design and process optimization. This article describes the physical and chemical models used in this technique and the current state of the art of the available software tools is reviewed. Moreover, the potential of equipment simulation will be highlighted by means of three recent examples from advanced quarter micron silicon process development. These include a vertical batch reactor for LPCVD of arsenic doped silicon oxide, a multi station tungsten CVD reactor, and a plasma reactor for silicon etching.

A gate oxide excess current model is described based on the phonon-assisted tunneling process of electrons into neutral traps. The influence on local electric field of charge of electrons trapped by neutral traps in gate oxide is simulated using a two-dimensional device simulator into which the new model is incorporated. FN current is suppressed with an increase in the neutral trap density to over 1019 cm-3. The calculated results reflect the endurance characteristics of flash memories in which erase/write operation speed depends on FN current.

A new concept of "an imperfect singular solution" is defined as an approximate solution which becomes a singular solution by adding a suitable small perturbation to the original equations. A numerical method is presented for proving the existence of imperfect singular solutions of nonlinear equations with guaranteed accuracy. A few numerical examples are also presented for illustration.

This paper proposes a new distributed connection establishment scheme involving several competing network providers in a multimedia telecommunications environment. This connection establishment scheme, which is based on the concept of open competitive bidding, enables mutual selection by users and network providers. By employing this proposed scheme, both network providers and users can pursue their own objectives, according to their own bidding and awarding strategies. In this paper, a simple bidding strategy for network providers is presented, and the effectiveness of this strategy is evaluated by means of computer simulation. It is shown that each network provider can improve its profit by adopting this strategy. In this paper, an example of utility functions for users is presented, and the effectiveness of the mechanism with which users can select a network provider is also evaluated by means of computer simulation. Each user can improve his/her utility by selecting an appropriate network provider based on this utility function.

The ATM Forum specifies several fairness criteria, thus the scheduling mechanisms should allocate enough bandwidth to each connection to achieve one of such fairness criteria. However, two fairness criteria (MCR plus equal share, maximum of MCR or Max-Min share) cannot be achieved by conventional scheduling mechanisms. In this letter, we have developed new scheduling mechanisms that achieve these fairness criteria. We also present simulation results to show that our mechanisms can allocate bandwidth fairly.

Recently, it is required to transfer continuous media over networks without QoS guarantee. In these networks, network congestion will cause transmission delay variance which degrades the quality of continuous media itself. This paper proposes a new protocol using a congestion control with two level rate control in the data transfer level and the coding level. It introduces a TCP-like congestion control mechanism to the rate control of data transfer level, which can detect the QoS change quickly, and adjust the coding rate of continuous media with time interval long enough for its quality. The performance evaluation through software simulation with multiplexing continuous media traffics and TCP traffics shows that the proposed protocol works effectively in the case of network congestion.

In this paper, we investigate the bit error rate (BER) performance of Direct Sequence-Code Division Multiple Access (DS-CDMA) systems under impulsive radio noise environments, and propose a novel DS-CDMA receiver which is designed to be robust against impulsive noise. At first, employing the Middleton's Class-A impulsive noise model as a typical model of impulsive radio noise, we discuss the statistical characteristics of impulsive radio noise and demonstrate that the quadrature components of impulsive noise are statistically dependent. Next, based on the computer simulation, we evaluate the BER performance of a conventional DS-CDMA system under a Class-A impulsive noise environment, and illustrate that the performance of the conventional DS-CDMA system is drastically degraded by the effects of the impulsive noise. To deal with this problem, motivated by the statistical dependence between the quadrature components of impulsive radio noise, we propose a new DS-CDMA receiver which can eliminate the effects of the channel impulsive noise. The numerical result shows that the performance of the DS-CDMA system under the impulsive noise environment is significantly improved by using this proposed receiver. Finally, to confirm the effectiveness of this proposed receiver against actual impulsive radio noise, we evaluate the BER performance of the DS-CDMA system employing the proposed receiver under a microwave oven (MWO) noise environment and discuss the robustness of the proposed receiver against MWO noise.

A distributed computing system consists of processing elements, communication links, memory units, data files, and programs. These resources are interconnected via a communication network and controlled by a distributed operating system. The distributed program reliability (DPR) in a distributed computing system is the probability that a program which runs on multiple processing elements and needs to retrieve data files from other processing elements will be executed successfully. This reliability varies according to 1) the topology of the distributed computing system, 2) the reliability of the communication edges, 3) the data files and programs distribution among processing elements, and 4) the data files required to execute a program. In this paper, we show that computing the distributed program reliability on a star distributed computing system is #P-complete. A polynomially solvable case is developed for computing the distributed program reliability when some additional file distribution is restricted on the star topology. We also propose a polynomial time algorithm for computing the distributed program reliability with approximate solutions when the star topology has no the additional file distribution.

This paper discusses the classification of targets buried in the underground by radar polarimetry. The subsurface radar is used for the detection of objects buried beneath the ground surface, such as gas pipes, cables and cavities, or in archeological exploration operation. In addition to target echo, the subsurface radar receives various other echoes, because the underground is inhomogeneous medium. Therefore, the subsurface radar needs to distinguish these echoes. In order to enhance the discrimination capability, we first applied the polarization anisotropy coefficient to distinguish echoes from isotropic targets (plate, sphere) versus anisotropic targets (wire, pipe). It is straightforward to find the man-made target buried in the underground using the polarization anisotropy coefficient. Second, we tried to classify targets using the polarimetric signature approach, in which the characteristic polarization state provides the orientation angle of an anisotropic target. All of these values contribute to the classification of a target. Field experiments using an ultra-wideband (250 MHz to 1 GHz) FM-CW polarimetric radar system were carried out to show the usefulness of radar polarimetry. In this paper, several detection and classification results are demonstrated. It is shown that these techniques improve the detection capability of buried target considerably.

The intermediate language (IL) modularizes a compiler into target processor independent and dependent parts, called the front-end and the back-end. By adding a new back-end, it is possible to port existing software from one processor to another. This paper presents a new efficient approach to achieve multiple targeting to quite different architectures using different processors as well, by translating from one IL into other existing ILs. This approach makes it possible to reuse existing back-ends. It has been successfully applied to a commercial-scale project for porting public switching system software. Since the target ILs were not predictable in advance, we provided an abstract syntax tree (AST) with attributes accessible by abstract data type (ADT) interface to convey the source language information from our front-end to back-ends. It was translated into several ILs that were developed independently. These translations made the compiler available in a very short time for different cross-target platforms and on several workstations we needed. The structure of this AST and the mapping to these ILs are presented, and retargeting cost is evaluated.

In this paper, we propose methods for testing the usability of graphical user interface (GUI) applications based on log files of user interactions. Log analysis by existing methods is not efficient because evaluators analyze a single log file or log files of the same user and then manually compare results. The methods proposed here solve this problem; the methods enable evaluators to analyze the log files of multiple users together by detecting interaction patterns that commonly appear in the log files. To achieve the methods, we first clarify usability attributes that can be evaluated by a log-based usability testing method and user interaction patterns that have to be detected for the evaluation. Based on an investigation on the information that can be obtained from the log files, we extract the attributes of clarity, safety, simplicity, and continuity. For the evaluations of clarity and safety, the interaction patterns that have to be detected include those from user errors. We then propose our methods for detecting interaction patterns from the log files of multiple users. Patterns that commonly appear in the log files are detected by utilizing a repeating pattern detection algorithm. By regarding an operation sequence recorded in a log file as a string and concatenating strings, common patterns are able to be detected as repeating patterns in the concatenated string. We next describe the implementation of the methods in a computer tool for log-based usability testing. The tool, GUITESTER, records user-application interactions into log files, generates usability analysis data from the log files by applying the proposed methods, and visualizes the generated usability analysis data. To show the effectiveness of GUITESTER in finding usability problems, we report an example of a usability test. In this test, evaluators could find 14 problems in a tested GUI application. We finally discuss the ability of the proposed methods in terms of its log analysis efficiency, by comparing the analysis/sequence time (AT/ST) ratio of GUITESTER with those of other methods and tools. The ratio of GUITESTER is found to be smaller. This indicates the methods make log analysis more efficient.

Multicasting functionality is an important criterion in judging the powerfulness and extendibility of ATM switches. Recently many multicast ATM switches have been proposed. They are mostly modified from unicasting switches. For such switches to support multicasting, they often need some additional components, e. g. , copy network, and numerous modifications on the original unicasting network. Although the multicasting is supported, the method is often inefficient and the architecture is complicated and costly. In this paper, we propose a new multicast ATM switch. In the proposed architecture, the nonblocking unicast network will not be modified. All that need is a simple external nonblocking multicast module. The external nonblocking multicast module will not delay the original nonblocking unicast network module, and the cost in hardware complexity for the external nonblocking multicasting module will be O(NK log K), where N is the switch size and K is the number of broadcast buses used in the multicast module.

The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC4025.

To design and develop user-oriented, flexible and distributed applications which can deal with various users' requirements, new technologies to manage, control and utilize the services of communication networks have to be provided. In this paper, the current challenges faced by large-scale distributed applications are discussed and a framework for the next generation network operation and management is presented on the basis of agent-based computing technologies. Examples of flexible distributed applications are presented to clarify the role of application-centric flexible network operation and management.

This paper discusses the implementation and cost- and performance- evaluations of a distributed processing network, called DONA-α, which is one of the possible physical networks mainly implementing connection-oriented public switched network functions corresponding to OSI layers 1 to 3. The first feature of the DONA-α network is that it separates a switching subsystem and a control subsystem of a conventional switching system and independently allocates them over distributed nodes as a switching node and a control node. Each DONA-α switching node is given a much smaller switching capacity than the switching subsystem of the conventional switching system and is located near subscribers. In contrast, each DONA-α control node has much higher performance than the control subsystem of the conventional switching system. This allows a large number of switching nodes to share the same control node, which controls their connection setups. This separation provides the network with greater flexibility and allows more effective utilization of network resources, such as control processors, switching fabrics, and transmission links, than ever before. The second feature of DONA-α is that it provides a network with network-wide distribution transparency. This allows network resources including software such as databases and application programs to be shared and therefore to be utilized in the network more easily and more efficiently. The results of a network performance simulation and cost calculation confirm the viability of the DONA-α network.