Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.

An upper bound on frame error rate (FER) for generalized concatenated convolutional codes (GCCC's) with iterative decoding is presented. The GCCC is a generalized concatenated code which consists of an inner binary convolutional code and outer Reed-Solomon codes. The FER bound is derived from the average weight enumerator of the inner code. We can optimize the configuration of the outer code since the FER bound can be easily computed. Some optimum outer code profiles will be shown. The results show that combination of GCCC and iterative decoding attains fairly small frame error probability (PB 10-13, Eb/N0 = 6 dB) with relatively simple component code (16-state convolutional code and Reed-Solomon code of length 32).

Even though information in ATM networks is handled as fixed-sized packets (cells), packet-based scheduling is still needed in ATM networks. This letter proposes a packet-based scheduling mechanism that is based on comparison between a packet-based queue and a virtual queue that represents the queue length provided by a cell-based scheduling mechanism. Simulation results showed that this proposed scheduling allocates the bandwidth fairly to each connection.

The transfer function of IIR all-pass filters is a rational function of ω. However, the optimization of such a rational function using the successive projections method, which has a wider range of application than the Remez algorithm, has not been presented. In this paper, we propose designing IIR all-pass filters using the successive projections method.

Recent years have seen great advances in our understanding and modeling of the coupled diffusion of dopants and defects in silicon during integrated circuit fabrication processes. However, the ever-progressing shrinkage of device dimensions and tolerances leads to new problems and a need for even better models. In this review, we address some of the advances in the understanding of defect-mediated diffusion, focusing on the equations and parameters appropriate for modeling of dopant diffusion in submicron structures.

This paper discusses the implementation and cost- and performance- evaluations of a distributed processing network, called DONA-α, which is one of the possible physical networks mainly implementing connection-oriented public switched network functions corresponding to OSI layers 1 to 3. The first feature of the DONA-α network is that it separates a switching subsystem and a control subsystem of a conventional switching system and independently allocates them over distributed nodes as a switching node and a control node. Each DONA-α switching node is given a much smaller switching capacity than the switching subsystem of the conventional switching system and is located near subscribers. In contrast, each DONA-α control node has much higher performance than the control subsystem of the conventional switching system. This allows a large number of switching nodes to share the same control node, which controls their connection setups. This separation provides the network with greater flexibility and allows more effective utilization of network resources, such as control processors, switching fabrics, and transmission links, than ever before. The second feature of DONA-α is that it provides a network with network-wide distribution transparency. This allows network resources including software such as databases and application programs to be shared and therefore to be utilized in the network more easily and more efficiently. The results of a network performance simulation and cost calculation confirm the viability of the DONA-α network.

As wireless communication is penetrating every corner of the globe, the optimum design and accurate analysis of RF, power semiconductor devices become one of the biggest challenges in EDA and TCAD (Technology CAD) tool development. The performance gauge for these devices is quite different from that for either digital or analog devices aimed at small-signal applications in that the power gain, efficiency, and distortion (or the range of linearity) are the utmost design concerns. In this article, the methodology and mathematical foundation for numerical analysis of large signal distortion at the device simulation level are discussed. Although the harmonic balance (HB) method has long been used in circuit simulation for large signal distortion analysis, the implementation of the same method in device simulation faces daunting challenges, among which are the tremendous computational cost and memory storage management. But the benefits from conducting such a device level simulation are also obvious--for the first time, the impact of technology and structural variation of device on large signal performance can directly be assessed. The necessary steps to make the HB analysis feasible in device simulation are outlined and algorithmic improvement to ease the computation/storage burden is discussed. The applications of the device simulator for various RF power devices, including GaAs MESFETs and silicon LDMOS (lateral diffusion MOS) are presented, and the insight gained from such an analysis is provided.

Measurement-based mathematical modeling is an attractive approach for simulating, accurately and efficiently, circuits based on active devices from a diverse range of constantly evolving processes and technologies. The principle of the measurement-based approach is that it is often most practical to characterize the device with various high-frequency measurements, and then mathematically transform the data to produce predictive device dynamical models for small-signal (linear) and large-signal (nonlinear) circuit design purposes. There are many mathematical, physical, and measurement considerations, however, that must be incorporated into any sound framework for successful measurement-based modeling. This paper will review some foundations of the subject and discuss some future trends. Review topics include constructing nonlinear constitutive relations from linear data parameterized by operating point and conservation laws including terminal charge conservation and energy conservation. Recent advances and trends will be discussed, such as pulsed I-V and pulsed S-parameter characterization with implications for electro-thermal and dispersive dynamical models, nonlinear wave-form measurements, and the relationship to some black-box behavioral modeling approaches.

In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

The full-band Monte Carlo technique is currently the most accurate device simulation method, but its usefulness is limited because it is very CPU intensive. This work describes efficient algorithms in detail, which raise the efficiency of the full-band Monte Carlo method to a level where it becomes applicable in the device design process beyond exemplary simulations. The k-space is discretized with a nonuniform tetrahedral grid, which minimizes the discretization error of the linear energy interpolation and memory requirements. A consistent discretization of the inverse mass tensor is utilized to formulate efficient transport parameter estimators. Particle scattering is modeled in such a way that a very fast rejection technique can be used for the generation of the final state eliminating the main cause of the inefficiency of full-band Monte Carlo simulations. The developed full-band Monte Carlo simulator is highly efficient. For example, in conjunction with the nonself-consistent simulation technique CPU times of a few CPU minutes per bias point are achieved for substrate current calculations. Self-consistent calculations of the drain current of a 60nm-NMOSFET take about a few CPU hours demonstrating the feasibility of full-band Monte Carlo simulations.

A device simulator that simulates device performance in the cyclic bias steady state was developed, and it was applied to GaAs hetero-junction FET (HJFET) pulse pattern effect. Although there is a large time-constant difference between the pulse signals and deep trap reactions, the simulator searches the cyclic bias steady states at about 30 iterations. A non-linear shift in the drain current level with the mark ratio was confirmed, which has been estimated from the rate equation of electron capture and emission based on Shockley-Read-Hall statistics for deep traps.

Equipment simulation can provide valuable support in reactor design and process optimization. This article describes the physical and chemical models used in this technique and the current state of the art of the available software tools is reviewed. Moreover, the potential of equipment simulation will be highlighted by means of three recent examples from advanced quarter micron silicon process development. These include a vertical batch reactor for LPCVD of arsenic doped silicon oxide, a multi station tungsten CVD reactor, and a plasma reactor for silicon etching.

A complex modular process flow was developed for PRISM technology to permit increased system integration. In order to combine the required functions--submicron CMOS Logic, Nonvolatile Memories, Precision Linear, and Power Drivers--on a monolithic silicon chip, a highly structured, systematic approach to process synthesis was developed. TCAD tools were used extensively for process design and verification. The 60 V LDMOS power transistor and the Flash memory cell built in the technology will be described to illustrate the process synthesis methodology.

Hawkins noise model is modified for HBT application. The non-ideal ideality factor of HBT is included in both dynamic resistance and noise figure equations. Emitter resistance is also included. The extraction method of noise resistance Rn is developed. Based on the method, a simple analytic equation of Rn is derived and experimentally verified. The effects of noise sources on minimum noise figure are analyzed. The dominant noise sources are the shot noises of emitter and collector currents. Generally, when the minimum noise figure is measured at various current levels, there exists an current level at which the slope of minimum noise figure curve is zero. The zero slope current level coincides with the current level at which the noise contribution of the emitter and collector shot noises including the cancellation by correlation of two sources is minimum. Parasitic resistance degrades output noise through the shot noise amplification with a minor effect of the thermal noise of itself.

A gate oxide excess current model is described based on the phonon-assisted tunneling process of electrons into neutral traps. The influence on local electric field of charge of electrons trapped by neutral traps in gate oxide is simulated using a two-dimensional device simulator into which the new model is incorporated. FN current is suppressed with an increase in the neutral trap density to over 1019 cm-3. The calculated results reflect the endurance characteristics of flash memories in which erase/write operation speed depends on FN current.

In this paper, we present two fast motion estimation techniques with adaptive variable search range using spatial and temporal correlation of moving pictures respectively. The first technique uses a frame difference between two adjacent frames which is used as a criterion for deciding search window size. The second one uses deviation between the past and the predicted current frame motion vectors which is also used as a criterion for deciding search window size. Simulation results show that these methods reduce the number of checking points while keeping almost the same image quality as that of full search method.

In this paper, quasi-Gaussian filter, quasi-median filter and locally adaptive filters are introduced. A new adaptive vector filter based on noise estimate is proposed to suppress Gaussian and/or impulse noise. To estimate the type and degree of noise corruption, a noise detector and an edge detector are introduced, and two key parameters are obtained to characterize noise in color image. After globally estimating the type and degree of noise corruption, different locally adaptive filters are properly chosen for image enhancement. All noisy images, used to test filters in experiments, are generated by PaintShopPro and Photoshop software. Experimental results show that the new adaptive filter performs better in suppressing noise and preserving details than the filter in Photoshop software and other filters.

In this paper, by making good use of the parallel-transit-evaluation algorithm and sparsity of the connection between neurons, a pipeline structure is successfully introduced to the sequential Boltzmann machine processor. The novel structure speeds up nine times faster than the previous one, with only the 12% rise in hardware resources under 10,000 neurons. The performance is confirmed by designing it using 1.2 µm CMOS process standard cells and analyzing the probability of state-change.

This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.

In this paper, near real time digital radiography system was implemented for the automatic verification of local errors between simulation plan and radiation therapy. Portal image could be acquired through video camera, image board and PC after therapy radiation was converted into light by a metal/fluorescent screen. Considering the divergence according to the distance between the source and the plate, we made a 340 340 12 cm3 basis point plate on which five rods of 4 cm height and 8 mm diameter lead (Pb) were built to display reference points on the simulator and the portal image. We converted the portal image into the binary image using the optimal threshold value which was gotten through the histogram analysis of the acquired portal image using the basis point plate. we got the location information of the iso-center and basis points from the binary image, and removed the systematic errors which were from the differences between the simulation plan and the portal image. Field size which was measured automatically by optimal threshold portal image, was verified with simulation plan. Anatomic errors were automatically detected and verified with the normalized simulation and the portal image by pattern matching method after irradiating a part of the radiation. Therapy efficiency was improved and radiation side effects were reduced by these techniques, so exact radiation treatment are expected.