In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, 8 times oversampling has about 2 dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits depending on the input data rate and input noise. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5 dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling in white noise dominant input data. The results were applied to the fabricated circuits to validate the analysis.

In this paper, a new digital chaos circuit which can generate multiple-scroll strange attractors is proposed. Being based on the piecewise-linear function which is determined by on-chip supervised learning, the proposed digital chaos circuit can generate multiple-scroll strange attractors. Hence, the proposed circuit can exhibit various bifurcation phenomena. By numerical simulations, the learning dynamics and the quasi-chaos generation of the proposed digital chaos circuit are analyzed in detail. Furthermore, as a design example of the integrated digital chaos circuit, the proposed circuit realizing the nonlinear function with five breakpoints is implemented onto the FPGA (Field Programmable Gate Array). The synthesized FPGA circuit which can generate n-scroll strange attractors (n=1, 2, 4) showed that the proposed circuit is implementable onto a single FPGA except for the SRAM.

Low-voltage technique for IC is getting one of the most important matters. It is quite difficult to realize a filter which can operate at 1 V or less because the base-emitter voltage of transistors can hardly be reduced. A design of a low-voltage continuous-time filter is presented in this paper. The basic building block of the filter is a pseudo-differential transconductor which has no tail current source. Therefore, the operating voltage is lower than that of an emitter-coupled pair. However, the common-mode (CM) gain of the transconductor is quite high and the CMRR is low. In order to reduce the CM gain, a CM feedback circuit is employed. The transconductance characteristic is expressed as the function of hyperbolic cosine. The designed filter is a fifth-order gyrator-C filter. The transconductor and the filter which has a fifth-order Butterworth lowpass characteristic are demonstrated by PSpice simulation. Transconductance characteristic, CMRR and stability of the transconductor are confirmed through the simulation. In the analysis of the filter, frequency response and offset voltage are examined. It is shown that the filter which has corner frequency of the order of megahertz can operate at a 1 V supply voltage.

This paper treats a fault detection/location of multi-processor systems, and we present a checking scheme based on Modified Processor-Data (MPD) graph with considering an error generation/propagation model for Algorithm-Based Fault Tolerant (ABFT) systems. The error propagation model considered here allows a computation result with multiple (more than one) erroneous inputs to be either erroneous or error-free. Also a basic algorithm for constructing checks for single-fault locatable/two-fault detectable ABFT systems based on the checking scheme is described with design examples.

A software system has dynamic adaptability if it can adapt itself to dynamically changing runtime environments. As open-ended distributed systems and mobile computing systems have spread widely, the need for software systems with dynamic adaptability increases. We propose a software model with dynamic adaptability called DAS and its description language LEAD++. The basic mechanism for dynamic adaptability is called adaptable procedure. An adaptable procedure is a special kind of generic procedures (functions) whose methods are selected based upon the state of its runtime environment. Furthermore, control mechanisms of adaptable procedures -- including method selection strategies -- are realized using generic procedures. This sort of reflective architecture enables us to write a dynamically adaptable software system in highly flexible, extensible, readable and maintainable way. LEAD++ is an object-oriented reflective language that provides adaptable procedures and their control mechanisms as its basic language functionalities. We are currently implementing a prototype of LEAD++ as a pre-processor of Java. Using LEAD++, we can systematically describe dynamically adaptable applets, mobile objects, etc.

In this paper, we propose an adaptive predictive coding method based on image segmentation for lossless compression. MAR (Multiplicative Autoregressive) predictive coding is an efficient lossless compression scheme. Predictors of the MAR model can be adapted to changes in the local image statistics due to its local image processing. However, the performance of the MAR method is reduced when applied to images whose local statistics change within the block-by-block subdivided image. Furthermore, side-information such as prediction coefficients must be transmitted to the decoder with each block. In order to enhance the compression performance, we improve the MAR coding method by using image segmentation. The proposed MAR predictor can be adapted to the local statistics of the image efficiently at each pixel. Furthermore, less side-information need be transmitted compared with the conventional MAR method.

Secret information stored in a tamperfree device is revealed during the decryption or signature generation processes due to fault-based attack. In this paper, based on the coding approach, we propose a new fault-resistant system which enables any fault existing in modular multiplication and exponentiation computations to be detected with a very high probability. The proposed method can be used to implement all crypto-schemes whose basic operations are modular multiplications for resisting both memory and computational fault-based attacks with a very low computational overhead.

In this paper, a novel variable-rate vector quantizer (VQ) design algorithm using fuzzy clustering technique is presented. The algorithm, termed fuzzy entropy-constrained VQ (FECVQ) design algorithm, has a better rate-distortion performance than that of the usual entropy-constrained VQ (ECVQ) algorithm for variable-rate VQ design. When performing the fuzzy clustering, the FECVQ algorithm considers both the usual squared-distance measure, and the length of channel index associated with each codeword so that the average rate of the VQ can be controlled. In addition, the membership function for achieving the optimal clustering for the design of FECVQ are derived. Simulation results demonstrate that the FECVQ can be an effective alternative for the design of variable-rate VQs.

A new concept of "an imperfect singular solution" is defined as an approximate solution which becomes a singular solution by adding a suitable small perturbation to the original equations. A numerical method is presented for proving the existence of imperfect singular solutions of nonlinear equations with guaranteed accuracy. A few numerical examples are also presented for illustration.

We propose a new inverse modeling method to extract 2D channel dopant profile in an MOSFET. The profile is extracted from threshold voltage (Vth) of MOSFETs with a series of gate lengths. The uniqueness of the extracted channel and drain profile is confirmed through test simulations. The extracted profile of actual 0.1 µm nMOSFETs explains reverse short channel effects (RSCE) of threshold voltage dependent on gate length including substrate bias dependence.

Electro-thermal characteristics of the Si MOSFET in transient state are reported using a non-isothermal device simulator where both the transistor's self-heating and the thermal influence of its neighboring devices are duly taken into account. The thermal influence is estimated using a three-dimensional thermal simulator. Based on this set-up, we predict time-dependent electro-thermal characteristics of the Si MOSFET at gate switching and its drain breakdown conditions. We show that the time delay between the electrical response and the lattice temperature rise, is significant and thus can not be neglected. In addition, we found that avalanche and thermal breakdown characteristics largely depend on the slope of the drain input voltage.

Since ATM network is a connection-oriented network, the operation for connectionless service is required for data service in it. There are many ways to support connectionless service in ATM network. They are ATM LAN Emulation, Classical IP and ARP over ATM, Indirect approach, Direct approach, and IP switch. It is known that Direct approach is suited for public network. The connectionless server supports connectionless service in Direct approach. There have been presented two kinds of methods, that is, streaming forwarding method and reassembly forwarding method, to forward the frames in the connectionless server. Reassembly forwarding method can work well with AAL5 which has better efficient characteristics than AAL3/4 in terms of easy use and fewer overheads. This paper proposes an algorithm that can decrease the loss of frame by a proposed buffer management working with AAL5. This paper also investigates the structure of the proposed connectionless server and its performance with the one of the conventional connectionless server through simulations. The proposed connectionless server shows a less frame loss and transfer delay than that of the conventional connectionless server.

The current Internet does not offer any quality of service guarantees or support to Internet multimedia applications such as Internet telephony and video-conferencing, due to the best-effort nature of the Internet. Their performance may be adversely affected by network congestion. Also, since these applications commonly employ the UDP transport protocol, which lacks congestion control mechanisms, they may severely overload the network and starve other applications. We present an overview of recent research efforts in developing adaptive delivery models for Internet multimedia applications, which dynamically adjust the transmission rate according to network conditions. We classify the approaches used to develop adaptive delivery models with brief descriptions of representative research work. We then evaluate the approaches based on important design issues and performance criteria, such as the scalability of the control mechanism, responsiveness in detecting and reacting to congestion, and ability to accommodate receiver heterogeniety. Some conclusions are developed regarding the suitability of particular design choices under various conditions.

This paper describes a defect detection method which automatically extracts defect information from complicated background LSI patterns. Based on a scanning electron microscope (SEM) image, the defects on the wafer are characterized in terms of their locations, sizes and the shape of defects. For this purpose, two image processing techniques, the Hough transform and wavelet transform, have been employed. Especially, the Hough Transform for circles is applied to non-circular defects for estimating the shapes of defects. By experiments, it has been demonstrated that the system is very effective in defect identification and will be used as an integral part in future automatic defect pattern classification systems.

This paper outlines the modeling requirements of integrated circuit (IC) fabrication processes that have lead to and sustained the development of computer-aided design of technology (i. e. TCAD). Over a period spanning more than two decades the importance of TCAD modeling and the complexity of required models has grown steadily. The paper also illustrates typical applications where TCAD has been powerful and strategic to IC scaling of processes. Finally, the future issues of atomic-scale modeling and the need for an hierarchical approach to capture and use such detailed information at higher levels of simulation are discussed.

This paper discusses the implementation and cost- and performance- evaluations of a distributed processing network, called DONA-α, which is one of the possible physical networks mainly implementing connection-oriented public switched network functions corresponding to OSI layers 1 to 3. The first feature of the DONA-α network is that it separates a switching subsystem and a control subsystem of a conventional switching system and independently allocates them over distributed nodes as a switching node and a control node. Each DONA-α switching node is given a much smaller switching capacity than the switching subsystem of the conventional switching system and is located near subscribers. In contrast, each DONA-α control node has much higher performance than the control subsystem of the conventional switching system. This allows a large number of switching nodes to share the same control node, which controls their connection setups. This separation provides the network with greater flexibility and allows more effective utilization of network resources, such as control processors, switching fabrics, and transmission links, than ever before. The second feature of DONA-α is that it provides a network with network-wide distribution transparency. This allows network resources including software such as databases and application programs to be shared and therefore to be utilized in the network more easily and more efficiently. The results of a network performance simulation and cost calculation confirm the viability of the DONA-α network.

Recent years have seen great advances in our understanding and modeling of the coupled diffusion of dopants and defects in silicon during integrated circuit fabrication processes. However, the ever-progressing shrinkage of device dimensions and tolerances leads to new problems and a need for even better models. In this review, we address some of the advances in the understanding of defect-mediated diffusion, focusing on the equations and parameters appropriate for modeling of dopant diffusion in submicron structures.

This paper describes a high-power and low-distortion AlGaAs/GaAs HFET amplifier developed for digital cellular base station system. We proved experimentally that distortion characteristics such as IMD (Intermodulation Distortion) or NPR (Noise Power Ratio) are drastically degraded when the absolute value of the drain bias circuit impedance at low frequency are high. Based on the experimental results, we have designed the drain bias circuit not to influence the distortion characteristics. The developed amplifier employed two pairs of pre-matched GaAs chips mounted on a single package and the total output-power was combined in push-pull configuration with a microstrip balun circuit. The push-pull amplifier demonstrated state-of-the-art performance of 140 W output-power with 11.5 dB linear gain at 2.2 GHz. In addition, it exhibited extremely low distortion performance of less than 30 dBc at two-tone total output-power of 46 dBm. These results indicate that the design of the drain bias circuit is of great importance to achieve improved IMD characteristics while maintaining high power performance.

This paper discusses the generalized mutual exclusion problem defined by H. Kakugawa and M. Yamashita. A set of processes shares a set of resources of an identical type. Each resource must be accessed by at most one process at any time. Each process may have different accessible resources. If two processes have no common accessible resource, it is reasonable to ensure a condition in resource allocation, which is called allocation independence in this paper, i. e. , resource allocation to those processes must be performed without any interference. In this paper, we define a new structure, sharing structure coterie. By using a sharing structure coterie, the resource allocation algorithm proposed by H. Kakugawa and M. Yamashita ensures the above condition. We show a necessary and sufficient condition of the existence of a sharing structure coterie. The decision of the existence of a sharing structure coterie for an arbitrary distributed system is NP-complete. Furthermore, we show a resource allocation algorithm which guarantees the above requirement for distributed systems whose sharing structure coteries do not exist or are difficult to obtain.

This paper investigates a relationship between accepting powers of two-way deterministic one-counter automata and one-pebble off-line deterministic Turing machines operating in space between loglog n and log n, and shows that they are incomparable.