Area-restricted illumination of light onto a voltage-biased single-electron tunnel junction array is modeled by reduced resistance of junctions, and its effects on current-voltage characteristics, charge distributions and potential profiles are calculated by a Monte Carlo method. The results show that photocurrent nearly proportional to the applied voltage is generated above a threshold voltage determined by Coulomb blockade effect. The photocurrent increases with increasing irradiated area, which is ascribed to reduction in total resistance of the circuit. Under irradiation, a characteristic charge distribution is formed, i. e. , negative and positive charge bumps are formed in the nodes at the dark and bright boundaries. The charge bumps serve to screen the electric field formed by the bias voltage and create almost a flat potential in the irradiated area. Furthermore, time-response of the charge distribution to a pulse irradiation is also studied. For high dark resistance, the charge bumps are sustained for a long period working as a memory of light. These results suggest feasibility of single-electron photonic devices such as photodetectors and photomemories.

Considering the pattern classification/recognition tasks, the influence of the activation function on fault tolerance property of feedforward neural networks is empirically investigated. The simulation results show that the activation function largely influences the fault tolerance and the generalization property of neural networks. It is found that, neural networks with symmetric sigmoid activation function are largely fault tolerant than the networks with asymmetric sigmoid function. However the close relation between the fault tolerance and the generalization property was not observed and the networks with asymmetric activation function slightly generalize better than the networks with the symmetric activation function. First, the influence of the activation function on fault tolerance property of neural networks is investigated on the XOR problem, then the results are generalized by evaluating the fault tolerance property of different NNs implementing different benchmark problems.

This letter proposes a Perfect-Reconstruction (PR) encryption scheme based on a PR QMF bank. Using the proposed scheme, signals can be encrypted and reconstructed perfectly by using two Periodically Time-Varying (PTV) digital filters respectively. Also we find that the proposed scheme has a "good" encryption effect and compares favorably with frequency scramble in the aspects of computation complexity, PR property, and degree of security.

An adaptive stability-growth (ASG) learning algorithm is proposed for improving, as much as possible, the stability of a Hopfield-type associative memory. While the ASG algorithm can be used to determine the optimal stability instead of the well-known minimum-overlap (MO) learning algorithm with sufficiently large lower bound for MO value, it converges much more quickly than the MO algorithm in real implementation. Therefore, the proposed ASG algorithm is more suitable than the MO algorithm for real-world design of an optimal Hopfield-type associative memory.

We propose a new method for verifying synchronous circuits using the Boyer-Moore Theorem Prover (BMTP) based on an efficient use of induction. The method contains two techniques. The one is the representation method of signals. Each signal is represented not as a waveform, but as a time parameterized function. The other is the mechanical transformation of the circuit description. A simple description of the logical connection of the components of a circuit is transformed into such a form that is not only acceptable as a definition of BMTP but also adequate for applying induction. We formalize the method and show that it realizes an efficient proof.

This paper presents two types of two-dimensional (2-D) adaptive beamforming algorithm which have high rate of convergence. One is a linearly constrained minimum variance (LCMV) beamforming algorithm which minimizes the average output power of a beamformer, and the other is a generalized sidelobe canceler (GSC) algorithm which generalizes the notion of a linear constraint by using the multiple linear constraints. In both algorithms, we apply a 2-D lattice filter to an adaptive filtering since the 2-D lattice filter provides excellent properties compared to a transversal filter. In order to evaluate the validity of the algorithm, we perform computer simulations. The experimental results show that the algorithm can reject interference signals while maintaining the direction of desired signal, and can improve convergent performance.

Gate performance for observing Coulomb oscillations and Coulomb diamonds are compared for two types of gated sub-µm double-barrier heterostructures. The first type of device contains modulation-doped barriers, whereas the second type of device contains a narrower band gap material for the well and no barriers with doped impurities. Both the Coulomb oscillations and Coulomb diamonds are modified irregularly as a function of gate voltage in the first type of device, while in the second type of device they are only systematically modified, reflecting atom-like properties of a quantum dot. This difference is explained in terms of the existence of impurities in the first type of device, which inhomogeneously deform the rotational symmetry of the lateral confining potential as the gate voltage is varied. The absence of impurities is the reason why we observe the atom-like properties only in the second type of device.

This letter gives a study of additionY=X+K mod 2w which is used in some cryptosystems as RC5. Our results enables us to express the differential and linear probability of addition as a function of addendK. To detect a good differential characteristics or linear approximation of a cryptosystem in which extended key is used as addend, we need to consider how the characteristics or approximations behave depending upon the value of the addend, which are clarified by our results.

We propose a novel opto-electronic memory device using a single quantum dot (QD) and a logic device using coupled QDs (CQD) which performs (N)AND and (N)OR operations simultaneously. In both devices, occupation/unoccupation by a single electron in a QD is viewed as a bit 1/0 and data input/output (I/O) is performed by irradiation/absorption of photons. The (N)AND/(N)OR operations are performed by the relaxation of the electronic system to the Fock ground state which depends on the number of electrons in the CQD. When the device is constructed of semiconductor nanostructures, the main relaxation process is LA-phonon emission from an electron. Theoretical analysis of the device shows that (i) the error probability in the final state converges with the probability with which the system takes excited states at thermal equilibrium, i. e. , depends only on the dissipation energy and becomes smaller as the dissipation energy becomes larger, and (ii) the speed of operation depends on both the dissipation energy and dissipative interactions and becomes slower as the dissipation energy becomes larger if LA-phonon emission is taken into account. If the QDs are InAs cubes with sides of 10 nm and they are separated by the AlSb barrier with a width of 10 nm, the speed of operation and the error probability are estimated to be about 1 ns and about 0. 2 at 77 K, respectively. The basic idea of the device is applicable to two-dimensional (2D) pattern processing if the devices are arranged in a 2D array.

In this paper, we propose an algorithm of classification by feature partitioning (CFP) which learns concepts in the batch mode. The proposed algorithm achieved almost the same predictive accuracies as the best results of a CFP algorithm presented by Guvenir and Sirin. However, our algorithm is not affected by parameters and the order of examples.

This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.

The Non-stop Service-Enhanceable Software (NOSES) platform was developed as part of our overall plan to establish a communications software platform that can be customized for use by various communications systems, such as STM, ATM and IN. The developed NOSES techniques are call-recovery restart, system file update, and on-line partial file modification, so called "Plug-in"; they were achieved by using dynamic program modification. A system-file update inevitably affects calls in service, despite efforts to save in-service calls by copying the call data from the old file to the new one. We therefore developed a different approach: Plug-in modification. This paper evaluates the applicability of the plug-in mechanism of the NOSES platform. Plug-in is a dynamic partial-file modification technique that does not affect calls in service in a communication switching system. In order to apply plug-in program modification widely, the static and dynamic properties of the modified software must be considered. Therefore, an applicability judgement matrix is introduced. The evaluated applicability of plug-in based on case studies and field data was about 60% for service feature additions and modifications. Thus, plug-in is effective for file maintenance of switching systems from the viewpoint of quick provisioning of new service features and bug fixes.

This paper proposes a new method for estimating route outage probability in non-regenerative repeater digital microwave radio systems. In this method, the route outage probability is estimated by various means, including path correlation of fading occurrence and C/N degradation corresponding to the number of non-regenerative repeater stations with and without demodulator devices. In the conventional method, the path correlation is treated as 0 and the C/N degradation is taken as a constant value on each path. To confirm the proposed method's effectiveness, a field test is carried out in which 16QAM signals pass through two non-regenerative repeater stations. The results obtained are in good agreement with the estimated outage probability.

The address-based queues are widely used in shared buffer ATM switches to guarantee the order of the cell delivery. In this paper, we propose an address-based queue mechanism to achieve an efficient use of the shared memory under a multicast service. In the switch, both cells and the address queues share the common memory. Each queue length changes flexibly according to the number of the stored cells. Our approach significantly reduces the cell loss probability as compared with the previously proposed approaches.

This paper extends left-incompatible term rewriting systems defined by Toyama et al. It is also shown that the functional strategy is normalizing in the class, where the functional strategy is the reduction strategy that finds index by some rule selection method and top-down and left-to-right lazy pattern matching method.

This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.

Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.

An MT connector assembly machine has been designed and developed. The connector assembly time using this machine is about 30% less than with the conventional method. The MT connectors assembled employing this machine have a low connection loss and stable mechanical characteristics.

We propose a spread-spectrum power line communication system considering the cyclic features of the noise in the lines. For this purpose, we model the noise as the sum of a time-invariant stationary process and two cyclostationary proceses, i.e., cyclic continuous noise and cyclic impulsive noise. The proposed system employs two different countermeasures to each of these two classes of cyclic noise. For the cyclic continuous noise, it uses multiple-processing-gain spread spectrum technique: the smaller processing gains are assigned for the periods with lower instantaneous noise power and the larger ones for the periods of higher noise power. Considering the cyclic impulsive noise, convolutional coding with interleaving is applied. In order to analyze the performance improvement due to the employment of multiple processing gains, we introduce a simple model of the continuous noise. The overall performance is evaluated by computer simulation with the actual noise wave-form measured in power lines.

A new flow algorithm is described on the basis of the primal-dual method, which is to be adopted dedicatedly for the regeneration of optimal layouts for functional cells of the standard-cell level. In advance of discussing this main theme, the present paper first outlines a practical scheme of reusing those layouts which have been once generated for functional cells in an old fabrication technology, and then formulates an optimization problem for regenerating optimal layouts of functional cells under the constraints incurred by the renewal of design rules. An efficient algorithm proposed here aims at solving this optimization problem with the use of solution concepts for the minimum cost flow problem. A part of experimental results is also shown, which indicates that the proposed altorithm is the fastest for this optimization problem.