A low power consumption 16-bit fixed point Digital Signal Processor (DSP) has been developed to realize a half-rate CODEC for the Personal Digital Cellular (PDC) system. Dual datapath architecture has been employed to execute multiply-accumulate (MAC) operations with a high degree of efficiency. With this architecture. 86.3% of total MAC operations in the Pitch Synchronous Innovation Code Excited Linear Prediction (PSI-CELP) program are executed in parallel, so that total instruction cycles are reduced by 23.1%. The area overhead for the dual datapath architecture is only 3.0% of the total area. Furthermore, in order to reduce power consumption, circuit design techniques are also extensively applied to RAMs. ROMs, and clock circuits, which consume the great majority of power. By reducing the number of precharging bit lines, a power reduction of 49.8% is achieved in RAMs, and above 40% in ROMs. By applying gated clock to clock lines, a power reduction of 5.0% is achieved in the DSP that performs the PSI-CELP algorithm. The DSP is fabricated in 0.5 µm single-poly, double-metal CMOS technology. The PSI-CELP algorithm for the PDC half-rate CODEC can operate at 22.5 MHz instruction frequency and 1.6 V supply voltage. resulting in a low-power consumption of 28 mW.

A miniature transceiver, including highly integrated MMIC front-end, for 1.9 GHz band personal handy phone system(PHS) has been developed. The terminal, adopting direct conversion transmitter and receiver technology, consists of four high-density RF circuit modules and a digital signal processing LSI with 2.7 V power supply. The four functional modules are a power amplifier, a transmitter,a receiver, and a frequency synthesizer. Each functional module includes one IC chip and passive LCR components connected with solder bumps on module substrate. The experimental miniature PHS handset has been fabricated to verify the design concepts of the miniature transceiver. The total volume of the developed PHS terminal is 60cc, including the 12cc front-end which comprises the four RF functional circuit modules. The air interface connection with the PHS base station simulator has been confirmed.

This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm9.09 mm die. It can realize an 11.2 kbps VSELP speech CODEC while consuming only 70 mW at 3.5 V Vdd.

I have examined factors for implementing a high-speed, low-power-consumption thermal head. In conventional thermal heads, a heat insulation layer is provided between the heating resistor and the radiator. I found it desirable to implement fast operation and low power consumption to lower the thermal conductivity of the heat insulation layer and to thin the heat insulation layer. I also found there is an optimum heat characteristic to the thickness of one heat insulation layer. I assumed polyimide as a material for the heat insulation layer which could materialize the hypothesis, and studied necessary items based on the thermal calculation. I manufactured a trial thermal head on the basis of this result and confirmed that our assumptions were correct. In addition, to confirm that the assumption is also ultimately correct, I fabricated a trial thermal head only consisting of a heating resistor and without a protective coat and a heat insulation layer. I confirmed that the structure with only the heating resistor exhibited excellent heat response and consumed less power necessary for heating.

This letter presents SAM, a multiplexer for ATM's circuit emulation services that can precisely control the cell clumping at the connection-level. Compared with a FIFO (First In First Out) multiplexer, it also improves the connection-level diffusion and CDV (Cell Delay Variation) performance. SAM can therefore significantly increase the number of connections accepted by CAC (Call Admission Control) procedures in the subsequent multiplexer.

A new mm-wave IC, constructed by flip-chip bonded heterojunction transistors and microstrip lines formed on Si substrate, has been proposed and demonstrated by using MBB (micro bump boding) technology. Millimeter-wave characteristics of the MBB region has been estimated by electro-magnetic field analysis. Good agreements between calculated and measured characteristics of this new IC (named MFIC: millimeter-wave flip-chip IC) have been obtained up to 60 GHz band. Several MFIC amplifiers with their designed performances have been successfully fabricated.

An experimental 3 V-only 4 Mb NAND Flash memory with 65 ns access time has been developed using a new charge pump circuit and novel circuit techniques such as folded bit-line architecture. By adopting a new program verify technique, programming time is reduced to 11 µs/Byte.

Low-power technology for front-end GaAs ICs and hybrid IC (HIC) for a mobile communication equipment will be presented. For low-power operation of GaAs front-end ICs, new techniques of the intermediate tuned circuits, the single-ended mixer, dualgate MESFETs, and the asymmetric self-aligned LDD process were investigated. The designed down-converter IC showed conversion gain of 21 dB, noise figure of 3.5 dB, 3rd-order intercept point in output level (IP3out) of 4.0 dBm, image-rejection ratio of 20 dB at 880 MHz, operating at 3.0 V of supply voltage and 5.0 mA of dissipation current. The down-converter IC was also designed for 1.9 GHz to obtain conversion gain of 20 dB, noise figure of 4.0 dB, IP3out of 4.0 dBm, image-rejection ratio of 20 dB at 3.0 V, 5.0 mA. The up-converter IC was designed for 1.9 GHz using the same topology of circuit and showed conversion gain of 15 dB, IP3out of 7.5 dBm, and 1 dB compression level of -8 dBm with -20 dBm of LO input power, operating at 3.0 V, 8.0 mA. Another approach to the low-power operation was carried out by HIC using the GaAs down-converter IC chip. The HIC was designed for 880 MHz to show conversion gain of 27 dB, noise figure of 3.3 dB, IP3out of 3.0 dBm, image-rejection ratio of 12 dB, at 2.7 V, 4.5 mA. The HIC measures only 8.0 mm6.0 mm1.2 mm.

This paper presents a new LP based optimal cell selection method. Optimal cell selection is useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle cycle time optimization. We also make a useful initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it can speed up a 13k-transistor circuit of a manual chip design by 17% without any increase of area.

This letter proposes a VP-shaper for ATM networks that controls the VC-level cell clumping. The new shaper is compared with a conventional shaper and is found to significantly increase CAC (Call Admission Control) efficiency and achieve high VP utilization gain. Hardware implementation based on a shared buffer and chained lists is presented and its feasibility is shown.

We can understand and recover a scene even from a picture or a line drawing. A number of methods have been developed for solving this problem. They have scarcely aimed to deal with scenes of multiple objects although they have ability to recognize three-dimensional shapes of every object. In this paper, challenging to solve this problem, we describe a method for deciding configurations of multiple objects. This method employs the assumption of coplanarity and the constraint of occlusion. The assumption of coplanarity generates the candidates of configurations of multiple objects and the constraint of occlusion prunes impossible configurations. By combining this method with a method of shape recovery for individual objects, we have implemented a system acquirig a three-dimensional information of scene including multiple objects from a monocular image.

This paper reports on the properties of thin-film thermal switches that are monolithically fabricated on high-Tc superconductive filter. Operating at a wide temperature range of 50-77 K, it was found that the switch could control the center frequency by -10 MHz with an increased insertion loss of less than 0.7 dB. In an on-off switching operation of filter characteristics using thin-film switches, power consumption was approximately 20 mW at 77 K, and the signal decay time as a switching speed was 30 ms at 76 K with a switch current of 70 mA. The decay time decreased exponentially as the switch current or the temperature setting increased.

This paper proposes a new fully-digitalized π/4-shift QPSK modulator consisting of a digital pulse shaping filter and a baseband quadrature modulator. By employing a novel digital filter configuration, the required filter memory is reduced to just 6.25% of the conventional one. Moreover, since the proposed baseband modulation scheme does not employ analog mixers or an analog 90 divider, a very accurate, high-stable and compact modulator is realized. It is shown that the proposed scheme achieves excellent low power consumption characteristics and is more suitable for digital LSIC implementation of personal communication terminals than a direct RF modulation scheme and an analog IF modulation scheme.

Acceleration techniques have been incorporated into the generalized method of characteristics (GMC) to perform transient analysis of uniform transmission lines, for the special case when the transmission lines are driven by digital signals. These techinques have been proved to improve the simulation speed to a great extent when the analysis is carried out using iterative waveform relaxation method. It has been identified that the load impedance connected to the transmission line has a bearing on the efficiency of one of these acceleration techniques. Examples of an RLCG line terminated with linear loads as well as nonlinear loads are given to illustrate the advantage of incorporating these acceleration techniques.

We applied a filip-chip-bonding technique to GHz-band SAW filters. The SAW filters mounted by the stud-bump-bonding (SBB) technique which is a kind of flip-chip-bonding technique showed almost the same frequency characteristics as those mounted by the conventional wire-bonding technique at 1.5 GHz. The SAW filter configuration, fabrication process using the SBB, and its electrical characteristics are described and discussed. The SBB technique has a lot of potential to reduce the size and weight even above GHz frequencies.

A new optical interconnection system suitable for high-speed ICs using a novel complementary optical interconnection technique has been developed. This system uses paired light sources and photodetectors for optical complementary operation, and greatly lowers the power consumption compared with conventional systems. Analyses and experimental results indicate that this system can operate in the gigabit range, and reduces power consumption to less than 20% of that in conventional systems at 1 Gb/s.

A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.

This paper describes a 16-bit microprocessor using circuit and process technology that realize static operation considering low-power consumption. The microprocessor so called V30HL achieved 4 times of performance per a unit power consumption as well as kept a complete software/hardware compatibility with standard 16-bit microprocessors. Also, the microprocessor operates in the range of DC-8 MHz for 2.7-5.5 V supply.