In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.

The paper argues that a radical shift in the market for communications services is emerging, driven by the mass availability of cheap bandwidth, computing and global mobility combined with the pervasive rise of Internet based data services. At the same time, the Operation Support Systems (OSS's*) that are essential in order to create business value from these technologies are lagging behind market need. The authors argue for a re-think of the humble management system into a complete software wrap-around of the network to deliver a value creation platform - as different from yesterday's OSS as the bakelite telephone is from today's tri-band mobile handsets. This software will be based on product standards, not paper ones and will require a major shift of gears from the position of today. This value creation platform will be built from advanced, component based software delivered through a very different market model to that of today. Much of this technology exists; we simply need critical mass behind a common approach. The discussion in this paper represents the personal views of the authors and does not necessarily represent the views of any organisation.

A new harmonic termination that controls the waveform of the drain current to be rectangular is developed for high-efficiency power amplifier modules. Its harmonic termination is a short circuit at the third harmonic and a non-short circuit at the second harmonic. It is found experimentally and confirmed by simulation that the load-matching condition at the third-order harmonic improves the efficiency of a transistor by more than 13%. By using this tuning, 57.7% power-added efficiency of the module is achieved at the output power of 29.9 dBm with ACP of -50 dBc, NACP of -65 dBc at 925 MHz and Vdd of 3.5 V.

A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.

A MMIC power amplifier operating with a single-supply (3.0 V) has been developed for 5.8 GHz Japanese Electronic Toll Collection (ETC) System. The present MMIC contains two FETs, matching circuits (input, intermediate and output matching circuits), and two drain bias circuits. High dielectric constant material SrTiO3 (STO) is used for by-pass and input coupling capacitors. Very small die size of 0.77 mm2 has been realized by using the STO capacitors and negative feedback circuit technology. High 1 dB output gain compression point (P1dB) of 13 dBm, high gain of 21.4 dB and low dissipation current of 41.3 mA have been achieved under 3.0 V single-supply condition.

Detecting the stuck-at-pass faults in the event-driven latches is the main difficult in testing latch based asynchronous pipeline. In this paper we proposed a parallel test structure to ease this problem.

In this paper, we describe the PS3 load distribution scheme. A target service is a transaction service consisting of multiple processes that communicate with each other. A target system consists of workstations connected by a LAN. PS3 determines the process allocation by estimating response times and throughputs. It allows us to set an upper limit of a response time, and to set lower and upper limits for the throughput of each service. PS3 tries to find a process allocation that provides the minimum response time under conditions set by the user in advance. We measured the response times and throughputs and compared the values with the estimated ones. The results show that PS3 provides an appropriate process allocation, and that calculated results agree well with the measured ones.

Miniaturized millimeter-wave HMIC amplifiers have been developed by using capacitively-coupled matching circuits (CCMC) and FETs with resistive source-stubs. CCMC includes FET's parasitic reactances, and is able to reduce the size of a matching circuit in a HMIC amplifier to about 1/3 of a conventional matching circuit using an open-circuited stub for matching and a quarter-wavelength coupled-line for d. c. blocking. The resistive source-stubs, which consist of two open-circuited stubs and a resistor, can improve the gain and stability of FETs at millimeter-wave frequencies. In this paper, design procedures of CCMC and the resistive source-stubs are described, and their usefulness has been confirmed experimentally through measurements of prototype V-band high-power HMIC amplifiers.

For cluster systems consisting of multiple nodes and shared servers which consist of an on-line and a backup server, we propose a hot-standby scheme of shared servers. In this scheme for shared servers, the shared servers have user data and control data. The on-line shared server sends only the control data to the backup server when it receives an update command. When the on-line shared server fails, the backup shared server reconstructs the shared data by using the latest control data sent from the on-line server and the user data sent from each node. We evaluated the system recovery time and the performance overhead for the hot-standby scheme. This enables the system recovery time to be shortened to 30 seconds and the performance overhead to be reduced to 2%.

The growth and saturation characteristics of an electromagnetic (EM) wave in a Smith-Purcell free-electron laser (FEL) with a Bragg cavity are investigated in detail with the aid of numerical simulation based upon the fluid model of the electron beam. To analyze the problem, a two-dimensional (2-D) model of the Smith-Purcell FEL is considered. The model consists of a planar relativistic electron beam and a parallel plate metallic waveguide, which has a uniform grating carved on one plate. For confinement and extraction of EM waves, a Bragg cavity is formed by a couple of reflector gratings with proper spatial period and length, which are connected at both ends of the waveguide. The results of numerical simulation show that a compact Smith-Purcell FEL can be realized by using a Bragg cavity composed of metallic gratings.

It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.

In a real-time system, it is required to reduce the response time to an interrupt signal, as well as the execution time of a Real-Time Operating System (RTOS). In order to satisfy this requirement, we have proposed a method of implementing some of the functionalities of an RTOS using hardware. Based on this idea, we have implemented a VLSI chip, called STRON (silicon TRON: The Realtime Operating system Nucleus), to enhance the performance of an RTOS, where the STRON chip works as a peripheral unit of any MPU. In this paper we describe the hardware architecture of the STRON chip and the performance evaluation results of the RTOS using the STRON chip. The following results were obtained. (1) The STRON chip is implemented in only about 10,000 gates when the number of each object (task, event flag, semaphore, and interrupt) is 7. (2) The task scheduler can execute within 8 clocks in a fixed period using the hardware algorithm when the number of tasks is 7. (3) Most of the basic µITRON system calls using the STRON chip can be executed in a fixed period of a few microseconds. (4) The execution time of a system call, measured by a multitask application program model, can be reduced to about one-fifth that in the case of the conventional software RTOS. (5) The total performance, including context switching, is about 2.2 times faster than that of the software RTOS. We conclude that the execution time of the part of the system call implemented by the STRON chip can almost be ignored, but the part of the interface software and context switching related to the architecture of a MPU strongly influence the total performance of an RTOS.

A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. In a semi-synchronous circuit, the minimum delay between registers may be critical with respect to the clock period of the circuit, while it does not affect the clock period of an ordinary synchronous circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio over the cycles in the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposing gate-level delay insertion method.

This paper presents a novel implication-based method for logic minimization in large-scale, multi-level networks. It significantly reduces network size through repeated addition and removal of redundant subnetworks, utilizing multi-signal implications and relationships among these implications. These are handled on a transitive implication graph, proposed in this paper, which offers the practical use of implications for logic minimization. The proposed method holds great promise for the achievement of an interactive logic design environment for large-scale networks.

This paper presents an algorithm for the scan-chain optimization problem in multiple-scan design methodology. The proposed algorithm, which consists of four phases, first determines pairs of scan-in and scan-out pins (Phase 1), and then assigns flip-flops to scan-paths by using a graph theoretical method (Phase 2). Next the algorithm decides connection-order of flip-flops in each scan-path by using TSP (Traveling Salesman Problem) heuristics (Phase 3), and finally exchanges flip-flops among scan-paths in order to reduce total scan-path length (Phase 4). Experiments using actual design data show that, for ten scan-paths, our algorithm achieved a 90% reduction in scan-test time at the expense of a 7% total scan-path length increase as compared with the length of a single optimized scan-path. Also, our algorithm produced less total scan-path length than other three possible algorithms in a reasonable computing time.

There are two approaches for formal verification of sequential designs or finite state machines: language containment checking and symbolic model checking. To verify designs of practical size, in these two approaches, designs are represented symbolically, in practice, by ordered binary decision diagrams. In the conventional algorithm for language containment checking, finite automata given as specifications are also represented symbolically. This paper proposes a new method, called partially explicit method for checking language containment. By representing states of finite automata given as specifications explicitly, this method can remove redundant computations, and as a result, provide better performance than the conventional method which uses the product machines of designs and specifications. The experimental results show that this approach is effective in checking language containment symbolically.

In this study, wave propagation phenomena of phase states are observed at van der Pol oscillators coupled by inductors as a ladder. For the case of 17 oscillators, interesting wave propagation phenomena of phase states are found. By using the relationship between phase states and oscillation frequencies, the mechanisms of the propagation and the reflection of wave are explained. Circuit experimental results agree well with computer calculated results qualitatively.

This paper deals with two-processor scheduling for a class of program nets, that are acyclic and SWITCH-less, and of which each node has unity node firing time. Firstly, we introduce a hybrid priority list L* that generates optimal schedules for the nets whose AND-nodes possess at most single input edge. Then we extend L* to suit for general program nets to give a new priority list L**. Finally, we use genetic algorithm to do the performance evaluation for the schedules generated by L** and show these schedules are quite close to optimal ones.

This paper describes a new millimeter-wave hybrid integrated circuit (HIC) technology which applies a thin film multi-layered dielectric substrate and flip-chip bonding technology employing stud bump bonding (SBB). We have previously proposed and demonstrated a novel HIC structure, named millimeter-wave flip-chip IC, (MFIC), applying an excellent dielectric material of benzocyclobutene (BCB) thin film and flip-chip bonding. In this paper, an advanced thin film multi-layer process using non-photosensitive BCB was newly developed. Characteristics of the transmission lines and the built-in MIM capacitor within the multi-layered structure were discussed. Furthermore, stud bump bonding was newly adapted to the MFIC as a flip-chip method, and the millimeter-wave characteristics of the bumps were examined. Using these technologies, we demonstrate characteristics of a miniaturized 25 GHz down converter MFIC. Our newly proposed HIC structure enabled us to bring down chip size to less than 1/3 of our conventional structure. Finally, we discuss future possibilities for high performance multi-chip-modules (MCMs) using SBB technology as a further improved HIC for compact millimeter-wave radio equipment.