Recent developments in computer technology allow us to analyze all the data in a huge database. Data mining is to analyze all the data in such a database and to obtain useful information for database users. One of the well-studied problems in data mining is the search for meaningful association rules in a market basket database which contains massive amounts of transactions. One way to find meaningful association rules is to find all the large itemsets first, and then to find meaningful association rules from the large itemsets. Although a number of algorithms for computing all the large itemsets have been proposed, the computational complexity of them is scarcely disscussed. In this paper, we show that it is NP-complete to decide whether there exists a large itemset that has a given cardinality. Also, we propose subclasses of databases in which all the meaningful association rules can be computed in time polynomial of the size of a database.

We report relations between invariant manifolds of saddle orbits (Lyapunov family) around a saddle-center equilibrium point and lowest periodic orbits on the two degree of freedom swing equation system. The system consists of two generators operating onto an infinite bus. In this system, a stable equilibrium point represents the normal operation state, and to understand its basin structure is important in connection with practical situations. The Lyapunov families appear under conservative conditions and their invariant manifolds constitute separatrices between trapped and divergent motions. These separatrices continuously deform and become basin boundaries, if changing the system to dissipative one, so that to investigate those manifolds is meaningful. While, in the field of two degree of freedom motions, systems with saddle loops to a saddle-center are well studied, and existence of transverse homoclinic structure of separatrix manifolds is reported. However our investigating system has no such loops. It is interesting what separatrix structure exists without trivial saddle loops. In this report, we focus on above invariant manifolds and lowest periodic orbits which are foliated for the Hamiltonian level.

A review of research, covering about 50 years, about random phenomena in nonlinear dynamical systems and the problems of modeling such phenomena using real (as contrasted to abstract, axiomatic) mathematics. Private views of the author concerning personalities and events.

We propose a new method to construct a four parameter family of quantum-mechanical point interactions in one dimension, which is known as all possible self-adjoint extensions of the symmetric operator T=-Δ C0(R \{0}). It is achieved in the small distance limit of equally spaced three neighboring Dirac's δ potentials. The strength for each δ is appropriately renormalized according to the distance and it diverges, in general, in the small distance limit. The validity of our method is ensured by numerical calculations. In general cases except for usual δ, the wave function discontinuity appears around the interaction and one can observe such a tendency even at a finite distance level.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

Though considerable effort has recently been devoted to hardware realization of one-dimensional chaotic systems, the influence of implementation inaccuracies is often underestimated and limited to non-idealities in the non-linear map. Here we investigate the consequences of sample-and-hold errors. Two degrees of freedom in the design space are considered: the choice of the map and the sample-and-hold architecture. Current-mode systems based on Bernoulli Shift, on Tent Map and on Tailed Tent Map are taken into account and coupled with an order-one model of sample-and-hold to ascertain error causes and suggest implementation improvements.

This paper treats the systematic design of chaos generators which are capable of generating continuous-time signals with prescribed probability density function and power density spectra. For a specific signal model a statistical analysis is performed such that the inverse problem, i. e. the calculation of the model parameters from prescribed signal characteristics, can be solved. Finally from the obtained model parameters and the model structure the signal generating system is constructed. The approach is illustrated by several examples.

A partial buffer sharing scheme is proposed as loss-priority control for a finite buffer with batch Poisson inputs under a whole batch acceptance rule. Customer and batch loss probabilities for high- and low-priority customers are derived under this batch acceptance rule using a supplementary variable method. A comparison of the partial buffer sharing scheme and a system without loss-priority control is made in terms of admissible offered load. Whole batch acceptance and partial batch acceptance rules are also compared in terms of admissible offered load.

A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.

This paper proposes applications of a code-division multiplexing technique to VLSI systems free from interconnection problems. We employ a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier to achieve efficient data transmission. Using orthogonal property of m-sequences, we can multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission with reduced interconnection. Also, randomness of m-sequences offers the high tolerance to interference (jamming), and suppression of dynamic range of signals while maintaining a sufficient signal-to-noise ratio (SNR). We demonstrate application examples of multiplex computing circuits, neural networks, and spread-spectrum image processing to show the advantages.

A resonant-tunneling-diode (RTD) based sense amplifier circuit design has been proposed for the first time to envision a very high-speed and low-power memory system that also includes refresh-free, compact RTD-based memory cells. By combining RTDs with n-type transistors of conventional complementary metal oxide semiconductor (CMOS) devices, a new quantum MOS (Q-MOS) family of logic circuits, having very low power-delay product and good noise immunity, has recently been developed. This paper introduces the design and analysis of a new QMOS sense amplifier circuit, consisting of a pair of RTDs as pull-up loads in conjunction with n-type pull-down transistors. The proposed QMOS sensing circuit exhibits nearly 20% faster sensing time in comparison to the conventional design of a CMOS sense amplifier. The stability analysis done using phase-plot diagram reveals that the pair of back-to-back connected static QMOS inverters, which forms the core of the sense amplifier, has meta-stable and unstable states which are closely related to the I-V characteristics of the RTDs. The paper also analyzes in details the refresh-free memory cell design, known as tunneling static random access memory (TSRAM). The innovative cell design adds a stack of two RTDs to the conventional one-transistor dynamic RAM (DRAM) cell and thereby the cell can indefinitely hold its charge level without any further periodic refreshing. The analysis indicates that the TSRAM cell can achieve about two orders of magnitude lower stand-by power than a conventional DRAM cell. The paper demonstrates that RTD-based circuits hold high promises and are likely to be the key candidates for the future high-density, high-performance and low-power memory systems.

This paper presents a new number representation called the Signed-Weight (SW) number system, which is useful for designing configurable counter-tree architectures for digital signal processing applications. The SW number system allows the unified manipulation of positive and negative numbers in arithmetic circuits by adjusting the signs assigned to individual digit positions. This makes possible the construction of highly regular arithmetic circuits without introducing irregular arithmetic operations, such as negation and sign extension in the two's complement representation. This paper also presents the design of a Field-Programmable Digital Filter (FPDF) architecture--a special-purpose FPGA architecture for high-speed FIR filtering--using the proposed SW arithmetic system.

The fact that there exists a core sinusoidal oscillator at the heart of Saito's double-screw hysteresis chaotic oscillator is demonstrated. By applying Bruton's transformation to the active linear part of the circuit, which is shown to be a classical LC-R negative resistor sinusoidal oscillator, an inductorless realization based on a frequency-dependent negative resistor (FDNR) is obtained. The LC-R sinusoidal oscillator is replaced by an FDNR-R oscillator. Furthermore, we show that chaotic behaviour can be preserved when a simple minimum component 2R-2C sinusoidal oscillator is used. Two different realizations of the non-monotone current-controlled hysteresis resistor, one of which is completely passive, are investigated. Experimental results of selected circuits, PSpice and numerical simulations are included.

The aim of this contribution is to take a further step in the study of the impact of chaos-based techniques on classical DS-CDMA systems. The problem addressed here is the sequence phase acquisition and tracking which is needed to synchronize the spreading and despreading sequences of each link. An acquisition mechanism is considered and analyzed in depth to identify analytical expressions of suitable system performance parameters, namely outage probability, link startup delay and expected time to service. Special chaotic maps are considered to show that the choice of spreading sequences can be optimized to accelerate and improve the spreading codes acquisition phase.

This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as (log2ppv + p(n-v) + 1) pn-1 to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.

In multi-media systems, the type of interactive communication channels is found almost everywhere and plays an important role, as well as the type of unilateral communication channels. In this report, we shall construct a fluctuation theory based on the concept of set-valued mappings, suitable for evaluation, control and operation of interactive communication channels in multi-media systems, complicated and diversified on large scales. Fundamental conditions for availability of such channels are clarified in a form of fixed point theorem for system of set-valued mappings.

Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.

Recently there have been several attempts to construct a Markov information source based on chaotic dynamics of the PLM (piecewise-linear-monotonic) onto maps. Study, however, soon informs us that Kalman's 1956 embedding of a Markov chain is to be highly appreciated. In this paper Kalman's procedure for embedding a prescribed Markov chain into chaotic dynamics of the PLM onto map is revisited and improved by using the PLM onto map with the minimum number of subintervals.

This paper presents the generator polynomial matrices and the upper bound on the constraint length of punctured convolutional codes (PCCs), respectively. By virtue of these properties, we provide the puncturing realizations of the good known nonsystematic and systematic high rate CCs.

A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.