This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.

In this paper, we propose a novel fault-tolerant multicast algorithm for n-dimensional wormhole routed hypercubes. The multicast algorithm will remain functional if the number of faulty nodes in an n-dimensional hypercube is less than n. Multicast is the delivery of the same message from one source node to an arbitrary number of destination nodes. Recently, wormhole routing has become one of the most popular switching techniques in new generation multicomputers. Previous researches have focused on fault-tolerant one-to-one routing algorithms for n-dimensional meshes. However, little research has been done on fault-tolerant one-to-many (multicast) routing algorithms due to the difficulty in achieving deadlock-free routing on faulty networks. We will develop such an algorithm for faulty hypercubes. Our approach is not based on adding physical or virtual channels to the network topology. Instead, we integrate several techniques such as partitioning of nodes, partitioning of channels, node label assignments, and dual-path multicast to achieve fault tolerance. Both theoretical analysis and simulation are performed to demonstrate the effectiveness of the proposed algorithm.

This paper proposes a novel sequential coherent preambleless demodulator that uses phase signals instead of complex signals in the automatic frequency control (AFC) and carrier recovery circuits. The proposed demodulator employs a phase-combined frequency error detection circuit and dual loop AFC circuit to achieve fast frequency acquisition and low frequency jitter. It also adopts an open loop carrier recovery scheme with a sample hold circuit after the carrier filter to ensure carrier signal stability within a packet. It is shown that the frame error rate performance of the proposed demodulator is superior, by 30%, to that offered by differential detection in a frequency selective Rayleigh fading channel. The hardware size of the proposed demodulator is about only 1/10 that of a conventional coherent demodulator employing complex signals.

In this paper, the bit error rate (BER) of 16 differential amplitude phase shift keying (16DAPSK) modems in future mobile communication system is derived analytically. The channel employed in this paper is the frequency-selective and fast Rayleigh fading channel, corrupted by cochannel interference (CCI) and additive white Gaussian noise (AWGN). Exact expressions for the probability distributions of the differential phase and amplitude ratio are derived for the BER calculation. The BER and optimum boundary are obtained for various channel conditions. In addition, the results for the BER in the presence of CCI are provided.

Three types of mechanisms were evaluated to determine their applicability to partially modifying an online switching system file and to creating a partial file during the debugging phase. First, the applicability of the basic plug-in mechanism, currently used in commercial switching systems, was evaluated by using data obtained from an initial implementation of PHS and ATM switching systems. It was found to be applicable irrespective of software type (call-processing or OA&M) and service type (PHS or ATM). It was also found to be applicable to both specification changes and service feature additions. Then, an extended plug-in mechanism that is enhanced to be more robust against complicated software behaviour was evaluated by simulation. It was found to cover cases where the basic plug-in mechanism is difficult to apply. Used together, these two mechanisms guarantee stable and effective file management of an online switching system. A plug-in for offline file creation was found to be applicable to almost all types of file modifications, except when the interface definition is significantly changed. These plug-in mechanisms can serve as the basis for managing the files in multimedia communication service systems.

In a mobile computing environment, in which communication channels are limited and have low-bandwidths, mobile transactions are long-lived and frequently disconnected with their wireless network in processing. Such peculiarities of mobile transactions make existing transaction scheduling schemes inadequate and raise new challenging research problems. In this paper, we propose a new scheduling scheme called OTS/MT (Optimistic Timestamp Scheme for Mobile Transactions) for mobile transaction scheduling. OTS/MT is based on an optimistic approach that is suitable for low data contention, and prevents indefinite postponement and cascading delay which are major drawbacks of the existing optimistic concurrency control scheme and the timestamp ordering scheme. In addition, the OTS/MT algorithm is inherently a deadlock-free scheduling scheme. In order to schedule mobile transactions, OTS/MT postpones the detection of conflict between mobile transactions until transaction commit time to improve the performance deterioration of TO. In this paper, we attempt to show that this application of optimism to TO is justified by way of simulation.

In this paper, we consider the steady state mean square error (MSE) analysis for 2-D LMS adaptive filtering algorithm in which the filter's weights are updated along both vertical and horizontal directions as a doubly-indexed dynamical system. The MSE analysis is conducted using the well-known independence assumption. First we show that computation of the weight-error covariance matrix for doubly-indexed 2-D LMS algorithm requires an approximation for the weight-error correlation coefficients at large spatial lags. Then we propose a method to solve this problem. Further discussion is carried out for the special case when the input signal is white Gaussian. It is shown that the convergence in the MSE sense occurs for step size range that is significantly smaller than the one necessary for the convergence of the mean. Simulation experiments are presented to support the obtained analytical results.

This paper is consisting of the two novel EMC technologies that we have been developed in our laboratory. The first is the technology for measuring the RF (Radio Frequency) nearby magnetic field and estimation of the RF current in the printed circuit board (PCB) by using the small loop antenna with multi-layer PCB structure developed by our laboratory. I introduce the application of our small loop antenna with its physical structure and the analysis of the nearby magnetic field distribution of the printed circuit board applying the discrete Wavelet analysis. We can understand the behavior of the digital circuit in detail, and we can also take measures to meet the specification about the electromagnetic radiation from the digital circuit from the higher order of priority by using these technologies. The second is our proposing novel technology for reducing the electromagnetic radiation from the digital equipment by taking notice of the improvement of the de-coupling in the PCB. We confirmed the remarkable effect of this technology by redesigning the motherboard of the small-sized computer.

In this paper, we propose an efficient and stable algorithm employing fuzzy logic for available bit rate (ABR) traffic. Large time-delay incurred in the feedback path and the statistical variation in the link capacity at the ATM node can cause instability or unfairness. The stability and fairness issues are discussed and the performance of the proposed mechanism is evaluated.

In order to reduce state explosion problem, techniques such as symbolic state space traversal and partial order reduction have been proposed. Combining these two techniques, however, seems difficult, and only a few research projects related to this topic have been reported. In this paper, we propose handling single place zero reachability problem of Petri nets by using both partial order reduction and symbolic state space traversal based on ZBDDs. We also show experimental results of several examples.

The author proposes a flow control scheme which derives the optimal packet transmission rate from the ACKs of the sending packets. The optimization is based on mathematical programming such as the extremal method and least-squares method. The author proves that the proposed method is fair when the RTT and thepacket length of each sender are the same. It is also shown that the sufficient condition for the proposed method to be optimal and stable generally holds true in packet networks. The performances are examined by computer simulations, and it is found that high throughput is obtained regardless of the network structure.

A novel method for the radiated immunity test is proposed. The method is to generate controlled electromagnetic fields applying in arbitrary directions to an under test. The fields rotate at a low speed controlled electrically so that the immunity characteristics may be known in more detail. The primal characteristics of the fields generated by a trial benchtop setup are investigated.

The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.

Acquisition of three-dimensional information of a real-world scene from two-dimensional images has been one of the most important issues in computer vision and image understanding in the last two decades. Noncontact range acquisition techniques can be essentially classified into two classes: Passive and active. This paper concentrates on passive depth extraction techniques which have the advantage that 3-D information can be obtained without affecting the scene. Passive range sensing techniques are often referred to as shape-from-x, where x is one of visual cues such as shading, texture, contour, focus, stereo, and motion. These techniques produce 2.5-D representations of visible surfaces. This survey discusses aspects of this research field and reviews some recent advances including video-rate range imaging sensors as well as emerging themes and applications.

This paper presents the technologies for over-40-Gbit/s operation of InP-based HEMT ICs for future optical communication systems. High-speed interconnection using low-permittivity benzocyclobutene (BCB) film as an inter-layer insulator decreases interconnection delay and results in high-speed operation of digital circuits. A static frequency divider and a 2 : 1 multiplexer using this novel interconnection demonstrate 49-GHz and 80-Gbit/s operation, respectively. Ultrahigh-speed digital/analog ICs fabricated using the HEMTs were used in 40 Gbit/s optical transmission experiment and showed good bit-error-rate performance. A novel two-step recess process for gate recess etching considerably improves the performance of InP-based HEMTs and is found to be promising for future ultrashort-gate devices.

It is confirmed by simulation that SOI-DRAMs can be operated at high speed by using the floating body structures. Several floating body effects are analyzed. It is described that the dynamic retention characteristics are not dominated by capacitive coupling and hole redistribution. And it is described that those characteristics are determined by the leakage current in the small pn-junction region of the floating body. Reducing pn junction leakage current is important for realizing a long retention time. If the pn junction leakage is suppressed to 10-18 A/µm, a dynamic retention time of 520 sec at a VBSG of 0.5 V can be achieved at 27. On those conditions, the refresh current of SOI-DRAMs is reduced by 54% compared with bulk-Si DRAMs.

Computational sensor (smart sensor, vision chip in other words) is a very small integrated system, in which processing and sensing are unified on a single VLSI chip. It is designed for a specific targeted application. Research activities of computational sensor are described in this paper. There have been quite a few proposals and implementations in computational sensors. Firstly, their approaches are summarized from several points of view, such as advantage vs. disadvantage, neural vs. functional, architecture, analog vs. digital, local vs. global processing, imaging vs. processing, new processing paradigms. Then, several examples are introduced which are spatial processings, temporal processings, A/D conversions, programmable computational sensors. Finally, the paper is concluded.

This letter presents a cryptographic key assignment scheme for dynamic access control in a hierarchy. A scheme for extending a previous cryptographic key assignment scheme to reduce the computation required for key generation and derivation algorithms is also proposed.

In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are reset, and the phase of the PLL frequency synthesizer is initialized and the phase synchronization is achieved. In the proposed method, since the ringing in the transient state does not occur, the output of the PLL frequency synthesizer converges to the target frequency at Ta and the frequency switching time is speeded up. The effectiveness of the proposed method will be confirmed by experimental results.

There are two dynamics issues in vision chips: (i) The temporal dynamics issue due to the parasitic capacitors in a CMOS chip, and (ii) the spatial dynamics issue due to the regular array of processing elements in a chip. These issues are discussed in [1]-[3] for the resistor network with only associated parasitic capacitances. However, in this paper we consider also parasitic inductances as well as parasitic capacitances for a more precise network dynamics model. We show that in some cases the temporal stability condition for the network with parasitic inductances and capacitances is equivalent to that for the network with only parasitic capacitances, but in general they are not equivalent. We also show that the spatial stability conditions are equivalent in both cases.