Network traffic characteristics impacts directly network performance, and resource allocation policies. In this work, we introduce a multi-agent system, that manages the performance of web servers with minimal cost of mirroring. In our proposed system each web server is viewed as a software agent that perceives its environment by monitoring its traffic. The goal of the agent is to manage the performance, using cooperative mirror servers, while minimizing the cost of mirroring. Communication between the agents enables each web server to decide about its future actions, which is whether to share its load with the cooperative mirror servers, and how much load to assign to them. The architecture of a software agent that is intended to manage the performance of a web server, is elaborated and its different modules are described. Also a set of cooperative agents is defined, that form a multi-agent system and is intended to assure maintaining the performance with minimal cost of mirroring. The experimental results presented in this article illustrates the effectiveness of the proposed system.

Integration of spot-size converters (SSCs) with semiconductor optical amplifiers (SOAs) that improves chip-fiber optical coupling is inevitable for realizing high performance SOA modules. In this paper SSCs that can be easily integrated with SOAs and have little influence on the polarization sensitivity have been studied. We found that polarization insensitive active width-tapered SSCs can be realized by an optimum waveguide design of tensile-strained bulk structures. The SOA module exhibited large fiber-to-fiber gain (> 19 dB), small polarization sensitivity (< 0.4 dB), high fiber-coupled saturation output power (> +11.7 dBm) and record low module noise figure (< 6.3 dB) for the signal wavelength range of 1530-1560 nm.

We propose a new method that can speed up the modular multiplication by physically partitioning the key size into two slices. By using LSB-first and MSB-first approach on two respective partitioned hardware module in parallel, we reduce the number of iterations in modular multiplication from k to k/2+1 for k-bit operands, and the resulting performance is doubled when contrasted with an implementation purely by LSB-first or MSB-first approach.

In this paper, we propose the multirate repeating method for alias free subband adaptive filters (AFSAFs) and consider its convergence property. It is shown that we can adjust the convergence speed and the final error of the adaptive filters by varying its two parameters according to the requirements of the applications where the method is applied. The proposed method has two parameters, namely, the number of channel and the number of repetition. We show that by increasing the number of channels we can reduce the final error, and this property is preferred when the signal-to-noise ratio (SNR) is low. On the other hand, we show that the convergence speed of the AFSAF approaches to that of the affine projection algorithm (APA) by increasing the number of repetition. Through the computer simulations, we show the effect of the proposed method.

A wavelet based algorithm for scalable video compression is described, with the main focus put on memory bandwidth reduction and efficient VLSI implementation. The proposed algorithm adopts a modified 2-D subband decomposition scheme in conjunction with a partial zerotree search for efficient Embedded Zerotree Wavelet coding. The experiment with the performance of the proposed algorithm in comparison with that of conventional DWT, MPEG-2, and JPEG demonstrates that the image quality of the proposed algorithm is consistently superior to that of JPEG, and our scheme can even outperform MPEG-2 in some cases, although it does not exploit the inter-frame redundancy. In spite of the performance inferiority to the conventional DWT, the proposed algorithm attains significant reduction of DWT memory requirements, enhancing a reasonable balance between implementation cost and image quality.

Achieving optimal performance with minimal complexity are conflicting problems encountered in constructing receivers. In this paper, to solve the problem, we propose sector beamed space hopping which utilizes a Viterbi equalizing receiver. Reduction of the number of RF circuit sets, system complexity and decreasing the computational burden of the Viterbi equalizer through the use of sector beamed space hopping is presented. This is achieved using a sector beamed antenna which limits the number of paths in the multipath channel environment. This paper describes each key component which comprises the system and discusses the application of FH-SS communication. The channel is assumed to be an industrial indoor propagation channel, such as those found in a factory, where high reliability is required and many complex multipaths exist. We confirm through simulation that Viterbi equalization using less computational complexity can be obtained. It is found that there exists a trade off between system complexity and performance. Through the discussion of power consumption, cost and BER performance, we show that the proposed system achieves acceptable performance while having a low system complexity.

In this paper, we review the progress in BiSrCaCuO-2212 Intrinsic Josephson junctions (IJJs) by summarizing our recent results in fabrication and high frequency experiments. Using a double-side fabrication process, a well defined number of intrinsic Josephson junctions in a well defined geometry can be fabricated. The junctions in the stack are quite homogeneous, and the power distribution of external irradiation among the junctions is even. Shapiro steps are clearly observed up to 2.5 THz, and the general condition for the occurrence of Shapiro steps at frequency frf is that it should be much greater than the plasma frequency fpl. Under certain conditions the Shapiro steps are zero-crossing, making some applications possible, such as quantum voltage standard etc.

We report the measurements on the ramp-edge type Josephson and quasiparticle tunnel junctions with the different interface angle geometry using high-Tc YBa2Cu3O7-y (YBCO) electrodes. The YBCO/I/Ag tunnel junctions with different crystal-interface boundary angles are fabricated for the investigation of zero bias conductance peak. The angle dependent zero bias conductance peak typical to a dx2-y2-wave superconductor is observable. For Josephson junctions, YBCO ramp-edge junctions with different ab-plane electrodes relatively rotated by 45are fabricated using a CeO2 seed-layer technique. The temperature dependence of the maximum Josephson current for YBCO/PBCO/YBCO junctions (PBCO: PrBa2Cu3O7-y) exhibits angle-dependent behavior, qualitatively different from the Ambegaokar-Baratoff prediction. Under microwave irradiation of 9 GHz, the Shapiro steps appear at integer and/or half integer multiples of the voltage satisfying Josephson voltage-frequency relation, whose behavior depends on the sample angle geometry. The results are reasonably interpreted by the dx2-y2-wave theory by taking the zero energy state into account.

The size dependent properties of the intrinsic Josephson junctions in Bi2Sr2CaCu2Oy single crystal mesas in the external magnetic field are studied. The mesas of (1-140) µm long with 7-29 junctions were fabricated and their current-voltage characteristics were measured in external magnetic field applied parallel to the CuO2 layers up to 0.16 T. In zero magnetic field, multiple resistive branches with large hysteresis were observed in the current-voltage characteristics for the fabricated mesas. Almost identical critical currents were also observed for all the junctions in each mesa. With applied magnetic field, Ic of the longer mesas showed a complex magnetic field dependence as compared to that of the short mesas (of about 1 µm in length). It was observed that the lower critical magnetic field of the junctions decreased and approached a constant value with increasing number of junctions and also with increasing length of the junctions. Similar magnetic behavior was obtained by numerical simulations based on coupled sine-Gordon equations for such stacked junctions.

Scaled models for an anatomical head model and a simple head model are used to investigate the effects of head size on SAR characteristics for a cellular phone exposure at 835 MHz. From the results, we can see that a larger head produces a higher localized SAR and a lower whole-head averaged SAR.

This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

We have designed the Half Adder (HA) circuit and the Carry Save Serial Adder (CSSA) circuit based on pipeline architecture. Our HA has the structure of a two-stage pipeline and consists of 160 Josephson Junctions (JJs). Our CSSA has the structure of a four-stage pipeline with a feedback loop and consists of 360 JJs. These circuits were fabricated by the NEC standard process. There are two issues which should be considered in the design. One is parameter spreads generated by the fabrication process and the other is leakage currents between the gates. We have introduced a parameter optimization method to deal with the parameter spreads. We have also inserted three stages of JTLs to reduce leakage currents. We have experimentally confirmed the correct operations of these circuits. The obtained bias margins were 33.1% for the HA and 24.6% for the CSSA.

We have developed a new torque magnetometer on the basis of a 4-K refrigerator. The system temperature can be lowered down to 1.5 K by pumping liquefied helium from a top loading sample space. A piezoresistor bridge on a Si cantilever is used to detect torque acting on a sample. A transverse magnetic field is supplied by a variable-field permanent magnet up to 10 kG. We find that a sensitivity of our torque magnetometer is Δ τ 10-10 Nm.

This paper presents a high-throughput VLSI architecture for LZFG data compression and decompression. To reduce the hardware cost and maintain both of the interior node and the leaf node numbering systems, we modify the original LZFG data structure. Compared to the original LZFG tree, the number of characters in our modified LZFG data structure must be greater than one to establish one new interior node down the root node into the new node. Meanwhile, this architecture employs a series of encoding cells with content addressable memory (CAM) to search the longest match and maintain the LZFG data tree during the encoding and decoding processes. By using the parallel design, the compressor and decompressor can keep a constant high bit rate to encode and decode one character per clock cycle, that is, it is directly proportional to the operating clock rate, but independent of the sizes of the word dictionary and the input file. By using 0.25 µm CMOS silicon technology, the operating clock rate can be as high as 85 MHz. Some untargeted encoding cells will be disabled to reduce the power consumption during the comparison operation. Therefore, this architecture can be easily applied in the high-speed real-time communication and data storage systems.

In this paper, we propose a turbo equalization scheme for GMSK signals with frequency detection. Although the channel is AWGN, there exists severe ISI (Inter-Symbol Interference) in the received signal due to the premodulation Gaussian baseband filter in the transmitter as well as the narrowband IF filter in the receiver. We regard these two filters as a real number inner convolutional encoder. The ISI equalizer for this inner encoder and the outer decoder for a RSC (Recursive Systematic Convolutional) code, are connected through a random (de-)interleaver. These inner and outer decoders generate the reliability values in terms of LLR (Log Likelihood Ratio), using MAP or SOVA algorithm with SISO (soft input and soft output). Moreover iterative decoding with the limitation of LLR values are employed between two decoders to achieve a turbo equalization for GMSK frequency detection. Through computer simulations, the proposed system shows the BER=10-5 at Eb/N0=8.8 dB, when we take BT=0.6 (IF filter bandwidth multiplied by symbol duration) with the iteration number of 3. This means 3.1 dB improvement compared with the conventional scheme where the inner ISI equalizer is concatenated with the outer hard decision Viterbi decoder.

A rapid Pseudo-Noise (PN) acquisition scheme is proposed. The proposed scheme consists of a phase alignment detector and Voltage Controlled Clock (VCC) loop. The VCC loop is used to control the phase update of the local PN signal. It has an auxiliary signal that provides the loop with two stable locking points as well as the direction of each phase update. The performance of the proposed scheme is evaluated by simulation. Results show that the proposed scheme acquires the phase two to three times faster than the conventional coherent serial scheme, and 1.5 times faster than of that in [10], at a small amount of additional hardware.

A new class of least-squares algorithms is presented for adaptive filtering. The idea is to use a fixed set of directions and perform line search with one direction at a time in a cyclic fashion. These algorithms are called Euclidean Direction Search (EDS) algorithms. The fast version of this class is called the Fast-EDS or FEDS algorithm. It is shown to have O(N) computational complexity and a convergence rate comparable to that of the RLS algorithm. Computer simulations are presented to illustrate the performance of the new algorithm.

In this paper, we discuss digital watermarking techniques besed on modifying the spectral coefficient of an image, classified into quantization-based and correlation-based watermarking techniques. We first present a model of the watermark embedding and extracting processes and examine the robustness of the watermarking system against common image processing. Based on the result, we clarify the reason why detection errors occur in the watermark extracting process and give a method for evaluating the performance of the watermarking system. And then we study an improvement of the watermark extracting process using the deconvolution technique and present some concluding remarks in the last section.

Despite the enormous power of present-day computers, digital systems cannot respond to real-world events in real time. Biological systems, however, while being built with very slow chemical transistors, are very fast in such tasks like seeing, recognizing, and taking immediate actions. This paper discusses the issue of how we can build real-time intelligent systems directly on silicon. An intelligent VLSI system inspired by a psychological brain model is proposed. The system stores the past experience in the on-chip vast memory and recalls the maximum likelihood event to the current input based on the associative processor architecture. Although the system can be implemented in a CMOS digital technology, we are proposing here to implement the system using circuits operating in the analog/digital-merged decision making principle. Low-level processing is done in the analog domain in a fully parallel manner, which is immediately followed by a binary decision to yield answers in digital formats. Such a scheme would be very advantageous in achieving a high throughput computation under limited memory and computational resources usually encountered in mobile applications. Hardware-friendly algorithms have been developed for real-time image recognition using the associative processor architecture and some experimental results are demonstrated.

This letter proposes a 3-D stereo endoscopic image processing system. Whereas a conventional 3-D stereo endoscopic system has simple monitoring functions, the proposed system gives doctors exact depth feelings by providing them depth value information, visualization, and stereo PACS viewer to aid an education, accurate diagnosis, a surgical operation, and to further apply in a robotic surgery.