We present a digital double relaxation oscillation SQUID (DROS) with a digital flux-locked-loop (FLL) circuit consisting of an up/down counter and a digital-to-analog (D/A) converter. The up/down counter was designed using 4 jucntion logic (4JL) gates operated with a 2-phase power system. The D/A converter was designed using an R-2R ladder-type D/A converter. We simulated the dynamic behavior of the digital DROS with a digital FLL circuit combined with the 5-bit ripple up/down counter and the D/A converter. Simulation results show correct flux-locked behavior and a high slew rate of 107Φ0/s for the digital DROS.

This paper describes a new algorithm for configuring the array of adders used to add the partial products in a multiplier circuit. The new algorithm reduces not only the number of half adders in an adder tree, but also the number of operands passed to the block generating the final product in a multiplier. The arrays obtained with this algorithm are smaller than Wallace's ones and have fewer outputs than Dadda's arrays. We show some evaluation figures and preliminary simulation results of 4, 8 and 16-bit tree configurations.

In this paper, we propose fast bitmap search algorithms to reduce the computational complexity of transform-based vector quantization (VQ) techniques, which achieve better quality in reconstructed images than the ordinary VQ. By removing the unlikely codewords in each step, the bitmap search method, which starts from the most significant bitmap then the successive significant ones, can save more than 90% computation of the ordinary transformed VQ. By applying to the singular value decomposition (SVD) VQ as an example, theoretical analyses and simulation results show that the proposed bitmap search methods dramatically reduce the computation and achieve invisible distortion in the reconstructed images.

A novel residue arithmetic algorithm using radix-2 signed-digit (SD) number representation is presented. By this representation, memoryless residue arithmetic circuits using SD adders can be implemented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a p-digit radix-2 SD number system is introduced to simplify the residue operation. For a modulus m, 2p-1 m 2p+2p-1-1, in a residue number system (RNS), the modulo m addition is performed by using two p-digit SD adders, one for the addition and one for the residue operation. Thus, the modulo m addition time is independent of the word length of operands. When m=2p or m= 2p 1, the modulo m addition is implemented by using only one SD adder. Moreover, a modulo m multiplier is constructed using a binary modulo m SD adder tree, and the modulo m multiplication can be performed in a time proportional to log 2 p. The VHDL implementation method for the presented algorithm is also discussed. The design and simulation results of some residue arithmetic circuits show that high speed residue arithmetic circuits can be obtained by the presented algorithms.

Multi-user uniquely decodable (UD) k-ary coding for the multiple-access adder channel is investigated. It is shown that a Tf+g+1-user UD k-ary affine code with code length f+g+1 can be obtained from two Tf-user and Tg-user UD k-ary affine codes. This leads to construct recursively a Tn-user UD k-ary affine code with arbitrary code length n. The total rate of the code tends to be higher than those of all the multi-user UD k-ary codes reported previously as the number of users increases.

Coding scheme for a noisy multiple-access adder channel is proposed. When a T-user δ-decodable affine code C is given a priori, a qT-user λ δ-decodable affine code C* is produced by using a q q matrix B satisfying BA=λ Iq q, e. g. , a Hadamard matrix or a conference matrix. In particular, the case of δ=1 is considered for the practical purposes. A (2n-1)-user uniquely decodable (δ=1) affine code Cn with arbitrary code length n is recursively constructed. When Cn plays a role of C, a q(2n-1)-user λ-decodable affine code C* is obtained. The code length and the number of users of C* are more flexible than those of the Wilson's code. The total rate of the λ-decodable code in this paper tends to be higher than that of the λ-decodable code by Wilson as the number of users increases.

This paper describes a new design method for multiply-adders able to process a large quantity of multimedia data. I propose a (signed digits)(unsigned digits) fixed-point multiply-add/subtract unit. The unit eliminates the problems caused by the critical one-bit arithmetic precision drop-off peculiar to the conventional (signed digits)(signed digits) fixed-point multiply scheme. By simultaneously counting in the carry-save form, based on 7-3 counters simultaneously inputting the accumulation terms and the add/sub operation terms of multiplication results, carries are propagated faster than in the conventional method.

This paper proposes a method to construct smaller binary decision diagrams for characteristic functions (BDDs for CFs). A BDD for CF represents an n-input m-output function, and evaluates all the outputs in O(n+m) time. We derive an upper bound on the number of nodes of the BDD for CF of n-bit adders (adrn). We also compare complexities of BDDs for CFs with those of shared binary decision diagrams (SBDDs) and multi-terminal binary decision diagrams (MTBDDs). Our experimental results show: 1) BDDs for CFs are usually much smaller than MTBDDs; 2) for adrn and for some benchmark circuits, BDDs for CFs are the smallest among the three types of BDDs; and 3) the proposed method often produces smaller BDDs for CFs than an existing method.

A T-user uniquely decodable (UD) code {C1,C2,,CT} over an integer set {0,1,,k} with arbitrary code length is developed for a multiple-access adder channel (MAAC). Each of the T users is equipped with two codewords, one of which is zero vector. The T-user UD code is used to identify users through the MAAC. It is shown that a T(f+g+1)-user UD code with code length f+g+1 can be arranged from two given T(f)-user and T(g)-user UD codes. This idea makes it possible to construct recursively a T-user UD code for an arbitrary code length n and a positive integer k. The T-user UD code includes the Jevticode.

A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-µm flash EEPROM technology.

A compact residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, {-2,-1,0,1,2} and {-3,-2,-1,0,1,2,3}, are introduced. The former is used for the input and output, and the later for the inner arithmetic circuit of the presented multiplier. Integers 4p and 4p 1 are used as moduli of residue number system (RNS), where p is a positive integer and both circuits for partial product generation and sum of the partial products can be efficiently constructed by using the multiple-valued current-mode circuits. The modulo m addition, m=4p or m=4p 1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary tree of the multiple-valued modulo m SD adders, and consequently the modulo m multiplication is performed in O(log p) time. The number of MOS transistors required in the presented residue arithmetic multiplier is about 86p2 + 66p.

Novel memory and several logic circuits utilizing the chaotic oscillations produced in SQUIDs are proposed. First, the oscillation modes that can be produced in a SQUID circuit are analyzed. The results of simulation for the SQUID show that there exist four types of oscillations: periodic, subharmonic, chaotic and relaxation oscillations. The bifurcation diagram of oscillation waveforms reveals that the hysteresis phenomena in the relation between the terminal voltage or the current and the external flux appear and that these phenomena can be used for a memory operation. Secondary, novel digital circuits such as memory, Exclusive-OR and full adder circuits are proposed by utilizing the chaotic oscillations. In these digital circuits the chaotic oscillations are made correspond to the logic "1," while the periodic and subharmonic oscillations are made to the logic "0." In order to investigate how these digital circuits perform their functions, computer simulations are made. The simulation results show that the right operations can be achieved.

Two algorithms for minimum cut linear arrangement of a class of graphs called p-q dags are proposed. A p-q dag represents the connection scheme of an adder tree, such as Wallace tree, and the VLSI layout problem of a bit slice of an adder tree is treated as the minimum cut linear arrangement problem of its corresponding p-q dag. One of the two algorithms is based on dynamic programming. It calculates an exact minimum solution within nO(1) time and space, where n is the size of a given graph. The other algorithm is an approximation algorithm which calculates a solution with O(log n) cutwidth. It requires O(n log n) time.

We have designed rapid single-flux-quantum (RSFQ) adder circuits using two different architectures: one is the conventional architecture employing globally synchronous clocking and the other is the data-driven self-timed (DDST) architecture. It has been pointed out that the timing margin of the RSFQ logic is very sensitive to the circuit parameter variations which are induced by the fabrication process and the device parameter uncertainty. Considering the physical timing in the circuits, we have shown that the DDST architecture is advantageous for realizing RSFQ circuits operating at very high frequencies. We have also calculated the theoretical circuit yield of the DDST adders and shown that a four-bit system operating at 10 GHz is feasible with sufficient operating margin, considering the present 1 kA/cm2 Nb Josephson technology.

This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.

The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

In this paper, a novel completion prediction adder is proposed. The basic concept is to predict the completion of an adder by investigating the inputs and generate completion signal for synchronization according to the completion prediction signal. This scheme greatly enhances the performance of an adder in both aspects of delay and hardware cost. Furthermore, the relative performance enhancement compared with representative synchronous adders increases as the word length of an adder becomes longer. For example, the delay-hardware product of SCPA for a 64-bit adder is 45.1% and 42.7% of those of binary carry look-ahead adder (BCLA) and binary tree carry look-ahead adder (BTCLA), respectively.

A high-speed silicon-on-insulator (SOI) of a 1/8 frequency divider and a 64-bit adder were realized using an optimized gate-overlapped LDD and a self-aligned titanium silicide (TiSi2) source-drain structure. The advantages of the delay time and power consumption were analyzed by circuit simulation. The maximum operation frequency of the SOI divider is 2.9 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than the bulk-Si divider. The power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. On the other hand, the speed of the SOI adder is 1.9 nsec at 3.3 V. The SOI adder speed is about 1.3 times faster than the bulk adder. The power consumption of the SOI adder is about 80% of that of the bulk divider. It was found that the high speed, low power features of the SOI divider were due to the pass transistor which had low junction capacitance and little substrate bias effects, in addition to the low wiring capacitance and low fanout capacitance compared to the bulk adder. As a result, it is suggested that SOI circuits using pass transistor have a potential for GHz level systems and it is expected they will be applied to handy communication systems and portable computers used in the multimedia era.

The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.

A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.