This letter presents the ideas and methods of the winning solution* for the Kaggle Algorithmic Trading Challenge. This analysis challenge took place between 11th November 2011 and 8th January 2012, and 264 competitors submitted solutions. The objective of this competition was to develop empirical predictive models to explain stock market prices following a liquidity shock. The winning system builds upon the optimal composition of several models and a feature extraction and selection strategy. We used Random Forest as a modeling technique to train all sub-models as a function of an optimal feature set. The modeling approach can cope with highly complex data having low Maximal Information Coefficients between the dependent variable and the feature set and provides a feature ranking metric which we used in our feature selection algorithm.

In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.

REMUS-II (REconfigurable MUltimedia System 2) is a coarse-grained dynamically reconfigurable computing system for multimedia and communication baseband processing. This paper proposes a real-time H.264 baseline profile encoder on REMUS-II. First, we propose an overall mapping flow for mapping algorithms onto the platform of REMUS-II system and then illustrate it by implementing the H.264 encoder. Second, parallel and pipelining techniques are considered for fully exploiting the abundant computing resources of REMUS-II, thus increasing total computing throughput and solving high computational complexity of H.264 encoder. Besides, some data-reuse schemes are also used to increase data-reuse ratio and therefore reduce the required data bandwidth. Third, we propose a scheduling scheme to manage run-time reconfiguration of the system. The scheduling is also responsible for synchronizing the data communication between tasks and handling conflict between hardware resources. Experimental results prove that the REMUS-MB (REMUS-II version for mobile applications) system can perform a real-time H.264/AVC baseline profile encoder. The encoder can encode CIF@30 fps video sequences with two reference frames and maximum search range of [-16,15]. The implementation, thereby, can be applied to handheld devices targeted at mobile multimedia applications. The platform of REMUS-MB system is designed and synthesized by using TSMC 65 nm low power technology. The die size of REMUS-MB is 13.97 mm2. REMUS-MB consumes, on average, about 100 mW while working at 166 MHz. To my knowledge, in the literature this is the first implementation of H.264 encoding algorithm on a coarse-grained dynamically reconfigurable computing system.

We present an Interactive Tabu Search (ITS) algorithm to reduce the evaluation load of Interactive Evolutionary Computation (IEC) users. Most previous IEC studies used an evaluation interface that required users to provide evaluation values for all candidate solutions. However, user's burden with such an evaluation interface is large. Therefore, we propose ITS where users choose the favorite candidate solution from the presented candidate solutions. Tabu Search (TS) is recognized as an optimization technique. ITS evaluation is simpler than Interactive Genetic Algorithm (IGA) evaluation, in which users provide evaluation values for all candidate solutions. Therefore, ITS is effective for reducing user evaluation load. We evaluated the performance of our proposed ITS and a Normal IGA (NIGA), which is a conventional 10-stage evaluation, using a numerical simulation with an evaluation agent that imitates human preferences (Kansei). In addition, we implemented an ITS evaluation for a running-shoes-design system and examined its effectiveness through an experiment with real users. The simulation results showed that the evolution performance of ITS is better than that of NIGA. In addition, we conducted an evaluation experiment with 21 subjects in their 20 s to assess the effectiveness of these methods. The results showed that the satisfaction levels for the candidates generated by ITS and NIGA were approximately equal. Moreover, it was easier for test subjects to evaluate candidate solutions with ITS than with NIGA.

The Coarse Grained Reconfigurable Architectures (CGRAs) are proposed as new choices for enhancing the ability of parallel processing. Data transfer throughput between Reconfigurable Cell Array (RCA) and on-chip local memory is usually the main performance bottleneck of CGRAs. In order to release this stress, we propose a novel data transfer strategy that is called Heuristic Data Prefetch and Reuse (HDPR), for the first time in the case of explicit CGRAs. The HDPR strategy provides not only the flexible data access schedule but also the high data throughput needed to realize fast pipelined implementations of various loop kernels. To improve the data utilization efficiency, a dual-bank cache-like data reuse structure is proposed. Furthermore, a heuristic data prefetch is also introduced to decrease the data access latency. Experimental results demonstrate that when compared with conventional explicit data transfer strategies, our work achieves a significant speedup improvement of, on average, 1.73 times at the expense of only 5.86% increase in area.

This paper presents an approach based on character recognition to searching for keywords in on-line handwritten Japanese text. It employs an on-line character classifier and an off-line classifier or a combined classifier, which produce recognition candidates, and it searches for keywords in the lattice of candidates. It integrates scores to individually recognize characters and their geometric context. We use quadratic discriminant function(QDF) or support vector machines(SVM) models to evaluate the geometric features of individual characters and the relationships between characters. This paper also presents an approach based on feature matching that employs on-line or off-line features. We evaluate three recognition-based methods, two feature-matching-based methods, as well as ideal cases of the latter and concluded that the approach based on character recognition outperformed that based on feature matching.

Object-oriented languages have recently become common, making register indirect jumps more important than ever. In object-oriented languages, virtual functions are heavily used because they improve programming productivity greatly. Virtual function calls usually consist of register indirect jumps, and consequently, programs written in object-oriented languages contain many register indirect jumps. The prediction of the targets of register indirect jumps is more difficult than the prediction of the direction of conditional branches. Many predictors have been proposed for register indirect jumps, but they cannot predict the jump targets with high accuracy or require very complex hardware. We propose a method that resolves jump targets by forwarding execution results. Our proposal dynamically finds the producers of register indirect jumps in virtual function calls. After the execution of the producers, the execution results are forwarded to the processor's front-end. The jump targets can be resolved by the forwarded execution results without requiring prediction. Our proposal improves the performance of programs that include unpredictable register indirect jumps, because it does not rely on prediction but instead uses actual execution results. Our evaluation shows that the IPC improvement using our proposal is as high as 5.4% on average and 9.8% at maximum.

For flexibility in supporting mobility and multihoming in edge networks and scalability of the backbone routing system, future Internet is expected to be based on the concept of ID/locator split. Heterogeneity Inclusion and Mobility Adaptation through Locator ID Separation (HIMALIS) has been designed as a generic future network architecture based on ID/locator split concept. It can natively support mobility, multihoming, scalable backbone routing and heterogeneous protocols in the network layer of the new generation network or future Internet. However, HIMALIS still lacks security functions to protect itself from various attacks during the procedures of storing, updating, and retrieving of ID/locator mappings, such as impersonation attacks. Therefore, in this paper, we address the issues of security functions design and implementation for the HIMALIS architecture. We present an integrated security scheme consisting of mapping registration and retrieval security, network access security, communication session security, and mobility security. Through the proposed scheme, the hostname to ID and locator mapping records can be securely stored and updated in two types of name registries, domain name registry and host name registry. Meanwhile, the mapping records retrieved securely from these registries are utilized for securing the network access process, communication sessions, and mobility management functions. The proposed scheme provides comprehensive protection of both control and data packets as well as the network infrastructure through an effective combination of asymmetric and symmetric cryptographic functions.

In our privious paper, we proposed an algorithm that determines delay times of a timed Petri net from the structural information of a signaling pathway, but Petri net structures containing cycles and inhibitory arcs were not considered. This paper provides conditions for cycle-contained Petri nets to have reasonable delay times. Furthermore, handling of inhibitory arcs are discussed in terms of the reaction rate of inhibitory interaction in signaling pathway, especially the conversion process of Petri net with inhibitory arc to the one without inhibitory arc is given.

Content-centric networking (CCN) is one of candidates being spotlighted as the technologies of the future Internet to solve the problems of the current Internet. Since DoS/DDoS attack is the most serious threat to the current Internet, this letter introduces the possibility of DoS/DDoS attack on CCN for the first time. And we introduce an attack method using fake-request packets and propose countermeasures in order to detect and/or react to CCN DoS/DDoS attack, and then analyze the result of our proposal.

This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor. The REPICP based on EPIC architecture overcomes the disadvantages of hardware-based superscalar and software-based Very Long Instruction Word (VLIW) and utilizes the cooperation of compiler and hardware to enhance Instruction-Level Parallelism (ILP). In REPICP, we propose the Optimized Lock-Step execution Model (OLSM) and instruction control pipeline method. We also propose reduced innovative methods to optimize the design. The REPICP is fabricated in Artisan 0.13 µm Nominal 1P8M process with 57 M transistors. The die size of the REPICP is 100 mm2 (1010), and consumes only 12 W power when running at 300 MHz.

We propose a new hidden vector encryption (HVE) scheme that we call a ciphertext-policy delegatable hidden vector encryption (CP-dHVE) scheme. Several HVE schemes have been proposed and their properties have been analyzed extensively. Nonetheless, the definition of the HVE has been left unchanged. We therefore reconsider it, and point out that the conventional HVE should be categorized as the key-policy HVE, because the vectors corresponding to the secret keys can contain wildcards (which specify an access policy) whereas those corresponding to the ciphertexts cannot contain them. We then formalize its dual concept, the ciphertext-policy HVE, and propose a concrete scheme. Then, as an application of our scheme, we propose a public-key encryption with conjunctive keyword search scheme that can be used in the hierarchical user systems. Our scheme is novel in that the ciphertext size grows logarithmically to the number of uses in the system, while that of a conventional scheme grows linearly.

One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs' working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+), which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256 KB LLC, 1.8% over the latest prefetcher throttling, and 0.5% over our previous CCCPO. Moreover, it showed superior stability compared to related works, while lowering the hardware cost.

Turbo codes and LDPC (Low-Density Parity-Check) codes are two of the most powerful error correction codes that can approach Shannon limit in many communication systems. But there are little architecture presented to support both LDPC and Turbo codes, especially by the means of ASIC. This paper have implemented a common architecture that can decode LDPC and Turbo codes, and it is capable of supporting the WiMAX, WiFi, 3GPP-LTE standard on the same hardware. In this paper, we will carefully describe how to share memory and logic devices in different operation mode. The chip is design in a 130 nm CMOS technology, and the maximum clock frequency can reach up to 160 MHz. The maximum throughput is about 104 Mbps@5.5 iteration for Turbo codes and 136 Mbps@10iteration for LDPC codes. Comparing to other existing structure, the design speed, area have significant advantage.

Bag of visual words is a promising approach to object categorization. However, in this framework, ambiguity exists in patch encoding by visual words, due to information loss caused by vector quantization. In this paper, we propose to incorporate patch-level contextual information into bag of visual words for reducing the ambiguity mentioned above. To achieve this goal, we construct a hierarchical codebook in which visual words in the upper hierarchy contain contextual information of visual words in the lower hierarchy. In the proposed method, from each sample point we extract patches of different scales, all of which are described by the SIFT descriptor. Then, we build the hierarchical codebook in which visual words created from coarse scale patches are put in the upper hierarchy, while visual words created from fine scale patches are put in the lower hierarchy. At the same time, by employing the corresponding relationship among these extracted patches, visual words in different hierarchies are associated with each other. After that, we design a method to assign patch pairs, whose patches are extracted from the same sample point, to the constructed codebook. Furthermore, to utilize image information effectively, we implement the proposed method based on two sets of features which are extracted through different sampling strategies and fuse them using a probabilistic approach. Finally, we evaluate the proposed method on dataset Caltech 101 and dataset Caltech 256. Experimental results demonstrate the effectiveness of the proposed method.

In this paper we study the ploblem whether the language D(1) of all d-primitive words can be generated by a contextual grammar. It is proved that D(1) can be generated neither by an external contextual grammar nor by an internal contextual grammar, and that it can be generated by a total contextual grammar with choice.

In this paper, a block-constrained trellis coded vector quantization (BC-TCVQ) algorithm is combined with an algebraic codebook to produce an algebraic trellis vector code (ATVC) to be used in ACELP coding. ATVC expands the set of allowed algebraic codebook pulse position, and the trellis branches are labeled with these subsets. The Viterbi algorithm is used to select the excitation codevector. A fast codebook search method using an efficient non-exhaustive search technique is also proposed to reduce the complexity of the ATVC search procedure while maintaining the quality of the reconstructed speech. The ATVC block code is used as the fixed codebook of AMR-NB (12.2 kbps), which reduces the computational complexity compared to the conventional algebraic codebook.

We propose a system to provide accurate data and timely medical services, unconstrained by location, through the use of a platform that can utilize mobile devices, interface with sensors and medical information systems. As the application of integrated platform, we aim to develop medical services that manage thrombolytic therapy for emergent stroke patients.

We propose a novel dynamic hierarchical optical path network architecture that achieves efficient optical fast circuit switching. In order to complete wavelength path setup/teardown efficiently, the proposed network adaptively manages waveband paths and bundles of optical paths, which provide virtual mesh connectivity between node pairs for wavelength paths. Numerical experiments show that operational and facility costs are significantly reduced by employing the adaptive virtual waveband connections.

Silver electrical contacts are separated at constant speed and break arcs are generated in a DC100 V–450 V/10 A resistive circuit. The transverse magnetic field of a permanent magnet is applied to the break arcs. Dependences of the arc duration, arc dwell time and arc lengthening time on the strength of the magnetic field and supply voltage are investigated. The characteristics of the re-ignition of the break arc are also discussed. Following results are shown. The arc duration D is increased due to the increase of the arc lengthening time tm when the supply voltage E is increased for each magnetic flux density Bx, because the arc dwell time ts is almost constant. The arc duration D is increased due to the increase of both of the arc lengthening time tm and the arc dwell time ts when the magnetic flux density Bx is decreased. The arc lengthening time tended to become long when the re-ignition of the break arc is occurred. The lengthening time tends to become longer when the duration tm1 from the start of the arc lengthening to the start of the re-ignition is increased. Re-ignitions occurred frequently when the magnetic flux density of the transverse magnetic field is increased and the supply voltage is increased.