Proxy cryptosystems are classified into proxy decryption systems and proxy re-encryption systems on the basis of a proxy's role. In this paper, we propose an ID-based proxy cryptosystem with revocability and hierarchical confidentialities. In our scheme, on receiving a ciphertext, the proxy has the rights to perform the following three tasks according to the message confidentiality levels of the sender's intention: (1) to decrypt the ciphertext on behalf of the original decryptor; (2) to re-encrypt the ciphertext such that another user who is designated by the original decryptor can learn the message; (3) to do nothing except for forwarding the ciphertext to the original decryptor. Our scheme supports revocability in the sense that it allows proxy's decryption and re-encryption rights to be revoked even during the valid period of the proxy key without changing the original decryptor's public information. We prove that our proposal is indistinguishable against chosen identity and plaintext attacks in the standard model. We also show how to convert it into a system against chosen identity and ciphertext attacks by using the Fujisaki-Okamoto transformation.

In multimedia communication, due to the limited computational capability of the personal information machine, a coder with low computational complexity is needed to integrate services from several media sources. This paper presents two efficient candidate schemes to simplify the most computationally demanding operation, the excitation codebook search procedure. For fast adaptive codebook search, we propose an algorithm that uses residual signals to predict the candidate gain-vectors of the adaptive codebook. For the fixed codebook, we propose a fast search algorithm using an energy function to predict the candidate pulses, and we redesign the codebook structure to twin multi-track positions architecture. Overall simulation results indicate that the average perceptual evaluation of speech quality (PESQ) score is degraded slightly, by 0.049, and our proposed methods can reduce total computational complexity by about 67% relative to the original G.723.1 encoder computation load, and with perceptually negligible degradation. Objective and subjective evaluations verify that the more efficient candidate schemes we propose can provide speech quality comparable to that using the original coder approach.

Carrier aggregation (CA) is one of the most important techniques for LTE-Advanced because of its capability to support a wide transmission bandwidth of up to 100 MHz and heterogeneous networks effectively while achieving backward compatibility with the Release 8 LTE. In order to improve the performance of control information transmission in heterogeneous networks, cross-carrier scheduling is supported, i.e., control information on one component carrier (CC) can assign radio resources on another CC. To convey the control information efficiently, a search space is defined and used in Release 8 LTE. In cross-carrier scheduling, the optimum design for the search space for different CCs is a paramount issue. This paper presents two novel methods for search space design. In the first method using one hash function, a user equipment (UE)-specific offset is introduced among search spaces associated with different CCs. Due to the UE-specific offsets, search spaces of different UEs are staggered and the probability that the search space of one UE is totally overlapped by that of another UE can be greatly reduced. In the second method using multiple hash functions, a novel randomization scheme is proposed to generate independent hash functions for search spaces of different CCs. Because of the perfect randomization effect of the proposed method, search space overlapping of different UEs is reduced. Simulation results show that both the proposed methods effectively reduce the blocking probability of the control information compared to existing methods.

Iterative synthesis methods for making aware of wire congestion are proposed for a multi-context dynamically reconfigurable processor (DRP) with a large number of processing elements (PEs) and programmable-wire connections. Although complex data-paths can be synthesized using the programmable-wire, its delay is long especially when wire connections are congested. We propose two iterative synthesis techniques between a high-level synthesizer (HLS) and the place & route tool to shorten the prolonged wire delay. First, we feed back wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten by 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on the congestion. The synthesis time was shorten to 1/3 causing delay improvement rate degradation at two points on average.

Although IP address lookup schemes using ternary content addressable memory (TCAM) can perform high speed packet forwarding, TCAM is much more expensive than ordinary memory in implementation cost. As a low-cost solution, binary search algorithms such as a binary trie or a binary search tree have been widely studied. This paper proposes an efficient IP address lookup scheme using balanced binary search with minimal entries and optimal prefix vectors. In the previous scheme with prefix vectors, there were numerous pairs of nearly identical entries with duplicated prefix vectors. In our scheme, these overlapping entries are combined, thereby minimizing entries and eliminating the unnecessary prefix vectors. As a result, the small balanced binary search tree can be constructed and used for a software-based address lookup in small-sized routers. The performance evaluation results show that the proposed scheme offers faster lookup speeds along with reduced memory requirements.

This paper proposes an efficient scheme for concurrent error detection for hardware implementations of the block cipher AES. In the proposed scheme, the circuit component for the round function is divided into two stages, which are used alternately for encryption (or decryption) and error checking in a pipeline. The proposed scheme has a limited overhead with respect to size and speed for the following reasons. Firstly, the need for a double number of clock cycles is eliminated by virtue of the reduced critical path. Secondly, the scheme only requires minimal additional circuitry for error detection since the detection is performed by the remaining encryption (or decryption) components within the pipeline. AES hardware with the proposed scheme was designed and synthesized by using 90-nm CMOS standard cell library with various constraints. As a result, the proposed circuit achieved 1.66 Gbps @ 12.9 Kgates for the compact version and 4.22 Gbps @ 30.7 Kgates for the high-speed version. These performance characteristics are comparable to those of a basic AES circuit without error detection, where the overhead of the proposed scheme is estimated to be 14.5% at maximum. The proposed circuit was fabricated in the form of a chip, and its error detection performance was evaluated through experiments. The chip was tested with respect to fault injection by using clock glitch, and the proposed scheme successfully detected and reacted to all introduced errors.

We propose a robust and efficient algorithm called ROCKET for clustering large-scale transaction databases. ROCKET is a divisive hierarchical algorithm that makes the most of recent hardware architecture. ROCKET handles the cases with the small and the large number of similar transaction pairs separately and efficiently. Through experiments, we show that ROCKET achieves high-quality clustering with a dramatic performance improvement.

This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.

In orthogonal frequency division multiple access (OFD-MA) systems, soft frequency reuse (SFR) and distributed antenna system (DAS) are two effective techniques to avoid excessive inter-cell interference (ICI). To gain the advantages of both, in this letter, we build a new cell architecture by jointly taking DAS and SFR into consideration to achieve the goal of high and well-balanced capacity. Furthermore, to rectify the shortfall in the literature, the capacity and outage probability in the multi-cell environment are derived by taking the complete channel effects into account, including the path loss, shadowing and Rayleigh fading. Simulations verify the superior performance and exactness of the analytical results.

In order to study the influences of contact opening speeds on arc extinction gap length characteristics, Ag contacts were operated to break DC inductive load currents from 0.1 A to 2.0 A at 14 V with contact opening speeds of 0.5 mm/s, 1 mm/s, 2 mm/s, 5 mm/s and 10 mm/s in a switching mechanism employing a stepping motor, and arc voltage waveforms were observed at each opening of the contacts. From the results, the average arc durations were determined at each current level under the respective contact opening speeds, and the average arc extinction gap lengths were calculated by multiplying the average arc duration value and the contact opening speed value. It was found that average arc durations showed no significant differences with increasing contact opening speeds. Thus, arc extinction gaps became larger at faster opening speeds in the inductive load conditions of this study.

This paper presents a software-based parallel cryptographic solution with a massive-parallel memory-embedded SIMD matrix (MTX) for data-storage systems. MTX can have up to 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. Furthermore, a next-generation SIMD matrix called MX-2 has been developed by expanding processing-element capability of MTX from 2-bit to 4-bit processing. These SIMD matrix architectures are verified to be a better alternative for processing repeated-arithmetic and logical-operations in multimedia applications with low power consumption. Moreover, we have proposed combining Content Addressable Memory (CAM) technology with the massive-parallel memory-embedded SIMD matrix architecture to enable fast pipelined table-lookup coding. Since both arithmetic logical operation and table-lookup coding execute extremely fast on these architectures, efficient execution of encryption and decryption algorithms can be realized. Evaluation results of the CAM-less and CAM-enhanced massive-parallel SIMD matrix processor for the example of the Advanced Encryption Standard (AES), which is a widely-used cryptographic algorithm, show that a throughput of up to 2.19 Gbps becomes possible. This means that several standard data-storage transfer specifications, such as SD, CF (Compact Flash), USB (Universal Serial Bus) and SATA (Serial Advanced Technology Attachment) can be covered. Consequently, the massive-parallel SIMD matrix architecture is very suitable for private information protection in several data-storage media. A further advantage of the software based solution is the flexible update possibility of the implemented-cryptographic algorithm to a safer future algorithm. The massive-parallel memory-embedded SIMD matrix architecture (MTX and MX-2) is therefore a promising solution for integrated realization of real-time cryptographic algorithms with low power dissipation and small Si-area consumption.

The paper is devoted to the experimental study of the arc plasma characteristics in SF6, N2 and CO2. To one flexible model of gas circuit breaker, short circuit experiments have been carried out considering the influence of contact gap (4–12 mm), gas pressure (1–5 atm), short circuit current (1–5 kA effective value) as well as gas species particularly. During the experiments, the arc image, arc current and arc voltage are recorded by the high speed camera, shunt and voltage transducer, respectively. It demonstrates that to the above mentioned three kinds of gases, the arc radius and arc voltage increase with the short circuit current and gas pressure normally; however, under the same experimental conditions, N2 arc holds the minimum arc radius and the maximum arc voltage, and the arc voltage of SF6 arc is the lowest.

Recently, photovoltaic power systems and electric vehicles have been commonly used. Therefore, the importance of DC (direct current) switching is expected to increase in the near future. The authors have been examining a method of evaluating the electrode loss of AgNi contacts for an electromagnetic contactor with a medium DC load current at a resistive circuit. In this study, the arc energy and electrode mass changes were investigated in more detail. We carried out experiments of 100,000 operations for an electromagnetic contactor at a load current of 5 A constant with a source voltage change from 100 to 160 V. The arc duration, contact resistance, arc energy, and electrode mass changes were measured. As a result, the arc duration was found out increase with the source voltage. In addition, the stationary cathode mass change (loss) increased proportion only to the total arc energy. However, the stationary cathode loss per unit arc energy decreased at the highest source voltage.

Using a self-developed ASTM test system of contact material electrical properties under low voltage (LV), small-capacity, the current-frequency variable and a photoelectric analytical balance, the electric performance comparison experiments and material weighing of silver-based electrical contact materials, such as silver/tungsten and silver/cadmium oxide contact materials, are completed under LV, pure resistive load and small current at 400 Hz/50 Hz. The surface profiles and constituents of silver/tungsten contact material were observed and analyzed by SEM and EDAX. Researches indicate that the form of the contact material arc burnout at 400 Hz is stasis, not an eddy flow style at 50 Hz; meanwhile, the area of the contact burnout at 400 Hz is less than that of 50 Hz, and the local ablation on the surface layer at 400 Hz is more serious. Comparing the capacities of the silver-based contact materials with different second element such as CAgW50, CAgNi10, CAgC4 and CAgCdO15 at 400 Hz, no matter what the performances of arc erosion resistance or welding resistance, it can be found that the capacities of the silver/tungsten material is the best.

An efficient pruning method is proposed for the infinity-norm sphere decoding based on Schnorr-Euchner enumeration in multiple-input multiple-output spatial multiplexing systems. The proposed method is based on the characteristics of the infinity norm, and utilizes the information of the layer at which the infinity-norm value is selected in order to decide unnecessary sub-trees that can be pruned without affecting error-rate performance. Compared to conventional pruning, the proposed pruning decreases the average number of tree-visits by up to 37.16% in 44 16-QAM systems and 33.75% in 66 64-QAM systems.

Silver electrical contacts are separated to generate break arcs in a DC48 V/6-24 A resistive circuit. The transverse magnetic field formed by a permanent magnet is applied to the break arcs. A series of experiments are carried out for two different experimental conditions. One condition is a constant contact separating speed while the magnetic flux density is changed to investigate the shortening effect of the arc duration. Another condition is a constant magnetic flux density while the contact separating speed is changed to investigate the changes in the arc duration and the contact gap when the break arc is extinguished. As a result, with constant separating speed, it is confirmed that the duration of break arcs is shortened by the transverse magnetic field and the break arcs are extinguished when the arc length reaches a certain value L. Under the condition of constant transverse magnetic field, (i) the arc duration is shortened by increasing the separation speed; (ii) the contact gap when the break arc is extinguished is almost constant when the separating speed v is sufficiently faster than 5 mm/s.

With measuring the arc current, arc voltage and arc images, the high-current air arc commutation process across the separated electrodes was investigated. It shows that the existence of a short stable arc in the gap may increase the current commutation time. According to the energy balance of the arc column, the conditions to maintain the short stable arc were introduced and the effects of the current limiting resistance on the current commutation process were discussed.

The dynamic encoding algorithm for searches (DEAS) is a recently developed algorithm that comprises a series of global optimization methods based on variable-length binary strings that represent real variables. It has been successfully applied to various optimization problems, exhibiting outstanding search efficiency and accuracy. Because DEAS manages binary strings or matrices, the decoding rules applied to the binary strings and the algorithm's structure determine the aspects of local search. The decoding rules used thus far in DEAS have some drawbacks in terms of efficiency and mathematical analysis. This paper proposes a new decoding rule and applies it to univariate DEAS (uDEAS), validating its performance against several benchmark functions. The overall optimization results of the modified uDEAS indicate that it outperforms other metaheuristic methods and obviously improves upon older versions of DEAS series.

To clarify how the occurrence of contact welding is related to the series of arc duration characteristics in consecutive make and break operations, electrical endurance tests were conducted on commercially available automotive relays, and the voltage waveforms of make and break arcs between the electrodes were recorded with LabVIEW. Experimental results indicate that welding may occur suddenly or randomly with increasing number of operations. A single arc or a group of make or break arcs with a long arc duration does not necessarily result in contact welding, but a group of longer make or break arcs within a narrow range of operation numbers can cause imminent contact welding (such an effect can be called the “group of longer arcing duration effect”). It is confirmed that contact welding may occur in both make and break operations, but the welding probability during make operations is much higher than that during break operations.

A low-complexity Reed-Solomon (RS) decoder design based on the modified Euclidean (ME) algorithm proposed by Truong is presented in this paper. Low complexity is achieved by reformulating Truong's ME algorithm using the proposed polynomial manipulation scheme so that a more compact polynomial representation can be derived. Together with the developed folding scheme and simplified boundary cell, the resulting design effectively reduces the hardware complexity while meeting the throughput requirements of optical communication systems. Experimental results demonstrate that the developed RS(255, 239) decoder, implemented in the TSMC 0.18 µm process, can operate at up to 425 MHz and achieve a throughput rate of 3.4 Gbps with a total gate count of 11,759. Compared to related works, the proposed decoder has the lowest area requirement and the smallest area-time complexity.