This letter proposes the use of a novel time-modulated array structure to estimate the direction of arrival (DOA). Such a time-modulated coprime array (TMCA) is obtained by exchanging a coprime array's phase shifter for a radio frequency (RF) switch. Compared with a traditional coprime array, the TMCA's structure is much simpler, and it has a higher degree of freedom and resolution compared with a time-modulated uniform linear array (TMULA) due to its exploitation of the virtual array's equivalent signals. Theoretical analysis and experimental results have validated the effectiveness of the proposed structure and method and have confirmed that a TMCA's DOA performance is better than that of a TMULA using the same number of antennas.

A model extraction attack is a security issue in deep neural networks (DNNs). Information on a trained DNN model is an attractive target for an adversary not only in terms of intellectual property but also of security. Thus, an adversary tries to reveal the sensitive information contained in the trained DNN model from machine-learning services. Previous studies on model extraction attacks assumed that the victim provides a machine-learning cloud service and the adversary accesses the service through formal queries. However, when a DNN model is implemented on an edge device, adversaries can physically access the device and try to reveal the sensitive information contained in the implemented DNN model. We call these physical model extraction attacks model reverse-engineering (MRE) attacks to distinguish them from attacks on cloud services. Power side-channel analyses are often used in MRE attacks to reveal the internal operation from power consumption or electromagnetic leakage. Previous studies, including ours, evaluated MRE attacks against several types of DNN processors with power side-channel analyses. In this paper, information leakage from a systolic array which is used for the matrix multiplication unit in the DNN processors is evaluated. We utilized correlation power analysis (CPA) for the MRE attack and reveal weight parameters of a DNN model from the systolic array. Two types of the systolic array were implemented on field-programmable gate array (FPGA) to demonstrate that CPA reveals weight parameters from those systolic arrays. In addition, we applied an extended analysis approach called “chain CPA” for robust CPA analysis against the systolic arrays. Our experimental results indicate that an adversary can reveal trained model parameters from a DNN accelerator even if the DNN model parameters in the off-chip bus are protected with data encryption. Countermeasures against side-channel leaks will be important for implementing a DNN accelerator on a FPGA or application-specific integrated circuit (ASIC).

In this work, we introduce notions of quantum frequency arrangements consisting of quantum frequency squares, cubes, hypercubes and a notion of orthogonality between them. We also propose a notion of quantum mixed orthogonal array (QMOA). By using irredundant mixed orthogonal array proposed by Goyeneche et al. we can obtain k-uniform states of heterogeneous systems from quantum frequency arrangements and QMOAs. Furthermore, some examples are presented to illustrate our method.

This paper summarizes our recent studies on architecture, photonic integration, system validation and networking performance analysis of a flexible low-latency interconnect optical network switch (Flex-LIONS) for datacenter and high-performance computing (HPC) applications. Flex-LIONS leverages the all-to-all wavelength routing property in arrayed waveguide grating routers (AWGRs) combined with microring resonator (MRR)-based add/drop filtering and multi-wavelength spatial switching to enable topology and bandwidth reconfigurability to adapt the interconnection to different traffic profiles. By exploiting the multiple free spectral ranges of AWGRs, it is also possible to provide reconfiguration while maintaining minimum-diameter all-to-all interconnectivity. We report experimental results on the design, fabrication, and system testing of 8×8 silicon photonic (SiPh) Flex-LIONS chips demonstrating error-free all-to-all communication and reconfiguration exploiting different free spectral ranges (FSR0 and FSR1, respectively). After reconfiguration in FSR1, the bandwidth between the selected pair of nodes is increased from 50Gb/s to 125Gb/s while an all interconnectivity at 25Gb/s is maintained using FSR0. Finally, we investigate the use of Flex-LIONS in two different networking scenarios. First, networking simulations for a 256-node datacenter inter-rack communication scenario show the potential latency and energy benefits when using Flex-LIONS for optical reconfiguration based on different traffic profiles (a legacy fat-tree architecture is used for comparison). Second, we demonstrate the benefits of leveraging two FSRs in an 8-node 64-core computing system to provide reconfiguration for the hotspot nodes while maintaining minimum-diameter all-to-all interconnectivity.

This paper presents a weighted spatial filter (WSF) design method based on direction of arrival (DOA) estimates for a novel array configuration called a sum and difference composite co-array. A sum and difference composite co-array is basically a combination of sum and difference co-arrays. Our configuration can realize higher degrees of freedom (DOF) with the sum co-array part at a calculation cost lower than those of the other sparse arrays. To further enhance the robustness of our proposed sum and difference composite co-array we design an optimal beam pattern by WSF based on the information of estimated DOAs. Performance of the proposed system and the DOA estimation accuracy of close-impinging waves are evaluated through computer simulations.

Intersymbol interference (ISI) is a significant source of degradation in many digital communication systems including our proposed non-far region communication system using large array antennas in the millimeter-wave band in which the main cause of ISI can be attributed to the path delay differences among the elements of an array antenna. This paper proposes a quantitative method to evaluate the ISI estimated from the measured near-field distribution of the array antenna. The influence of the uniformity in the aperture field distribution in ISI is discussed and compared with an ideally uniform excitation. The reliability of the proposed method is verified through a comparison with another method based on direct measurements of the transmission between the actual antennas. Finally, the signal to noise plus interference is evaluated based on the estimated ISI results and ISI is shown to be the dominant cause of the degradation in the reception zone of the system.

Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.

The sidelobe level at tilts around 30-40 degrees in both the E and H planes due to a tapered excitation of units of 2×2 radiation slots is suppressed by introducing slit layers over a corporate-feed waveguide slot array antenna. The slit layers act as averaging the excitation of the adjacent radiating slots for sidelobe suppression in both planes. A 16×16-element array in the 70GHz band is fabricated. At the design frequency, the sidelobe levels at tilts around 30-40 degrees are suppressed from -25.4dB to -31.3dB in the E-plane and from -27.1dB to -38.9dB in the H-plane simultaneously as confirmed by measurements. They are suppressed over the desired range of 71.0-76.0GHz frequencies, compared to the conventional antenna.

Reference current used in sense amplifiers is a crucial factor in a single-end read manner for emerging memories. Dummy cell average read scheme uses multiple pairs of dummy cells inside the array to generate an accurate reference current for data sensing. The previous research adopts current mirror sense amplifier (CMSA) which is compatible with the dummy cell average read scheme. However, clamped bit-line sense amplifier (CBLSA) has higher sensing speed and lower power consumption compared with CMSA. Therefore, applying CBLSA to dummy cell average read scheme is expected to enhance the performance. This paper reveals that direct combination of CBLSA and dummy cell average read scheme leads to sense margin degradation. In order to solve this problem, a new array design is proposed to make CBLSA compatible with dummy cell average read scheme. Current mirror structure is employed to prevent CBLSA from being short-circuited directly. The simulation result shows that the minimum sensible tunnel magnetoresistance ratio (TMRR) can be extended from 14.3% down to 1%. The access speed of the proposed sensing scheme is less than 2 ns when TMRR is 70% or larger, which is about twice higher than the previous research. And this circuit design just consumes half of the energy in one read cycle compared with the previous research. In the proposed array architecture, all the dummy cells can be always short-circuited in totally isolated area by low-resistance metal wiring instead of using controlling transistors. This structure is able to contribute to increasing the dummy cell averaging effect. Besides, the array-level simulation validates that the array design is accessible to every data cell. This design is generally applicable to any kinds of resistance-variable emerging memories including STT-MRAM.

We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.

This paper presents a three-dimensional (3D) spatial localization algorithm by using multiple one-dimensional uniform linear arrays (ULA). We first discuss geometric features of the angle-of-arrival (AOA) measurements of the array and present the corresponding principle of spatial cone angle intersection positioning with an angular measurement model. Then, we propose a new positioning method with an analytic study on the geometric dilution of precision (GDOP) of target location in different cases. The results of simulation show that the estimation accuracy of this method can attain the Cramér-Rao Bound (CRB) under low measurement noise.

An analytic expression of the Capon spectrum is derived for two uncorrelated incident signals. On the basis of this theoretical formulation, we discuss the effect of a factor arising from the inner product of mode vectors with respect to the incident angles, which compromises the resolution. We show numerical examples to demonstrate the effect that the inner product of mode vectors has on the shape of the Capon spectrum.

This paper presents a two-dimensional (2D) DOA algorithm for double L-shaped arrays. The algorithm is applied to the underwater environment for eliminating the performance error caused by the sound speed uncertainty factor. By introducing the third dimensional array, the algorithm eliminates the sound velocity variable in the depression angle expression, so that the DOA estimation no longer considering the true value of unknown sound velocity. In order to determine the parameters of a three-dimensional array, a parameter matching method with the double L-shaped array is also proposed. Simulations show that the proposed algorithm outperforms the conventional 2D-DOA estimation algorithm in unknown sound velocity environment.

A paradigm shift toward edge computing infrastructures that prioritize small footprint and scalable/easy-to-estimate performance is increasing. In this paper, we propose the following to improve the footprint and the scalability of systolic arrays: (1) column multithreading for reducing the number of physical units and maintaining the performance even for back-to-back floating-point accumulations; (2) a cascaded peer-to-peer AXI bus for a scalable multichip structure and an intra-chip parallel local memory bus for low latency; (3) multilevel loop control in any unit for reducing the startup overhead and adaptive operation shifting for efficient reuse of local memories. We designed a systolic array with a single column × 64 row configuration with Verilog HDL, evaluated the frequency and the performance on an FPGA attached to a ZYNQ system as an AXI slave device, and evaluated the area with a TSMC 28nm library and memory generator and identified the following: (1) the execution speed of a matrix multiplication/a convolution operation/a light-field depth extraction, whose size larger than the capacity of the local memory, is 6.3× / 9.2× / 6.6× compared with a similar systolic array (EMAX); (2) the estimated speed with a 4-chip configuration is 19.6× / 16.0× / 8.5×; (3) the size of a single-chip is 8.4 mm2 (0.31× of EMAX) and the basic performance per area is 2.4×.

A convolutional neural network (CNN) for broadband direction of arrival (DOA) estimation of far-field electromagnetic signals is presented. The proposed algorithm performs a nonlinear inverse mapping from received signal to angle of arrival. The signal model used for algorithm is based on the circular antenna array geometry, and the phase component extracted from the spatial covariance matrix is used as the input of the CNN network. A CNN model including three convolutional layers is then established to approximate the nonlinear mapping. The performance of the CNN model is evaluated in a noisy environment for various values of signal-to-noise ratio (SNR). The results demonstrate that the proposed CNN model with the phase component of the spatial covariance matrix as the input is able to achieve fast and accurate broadband DOA estimation and attains perfect performance at lower SNR values.

In the theory of orthogonal arrays, an orthogonal array (OA) is called schematic if its rows form an association scheme with respect to Hamming distances. In this paper, we study the Hamming distances of any two rows in an OA, construct some schematic OAs of strength two and give the positive solution to the open problem for classifying all schematic OAs. Some examples are given to illustrate our methods.

This letter presents an improved hybrid direction of arrival (DOA) estimation scheme with computational efficiency for massive uniform linear array. In order to enhance the resolution of DOA estimation, the initial estimator based on the discrete Fourier transform is applied to obtain coarse DOA estimates by a virtual array extension for one snapshot. Then, by means of a first-order Taylor series approximation to the direction vector with the one initially estimated in a very small region, the iterative fine estimator can find a new direction vector which raises the searching efficiency. Simulation results are provided to demonstrate the effectiveness of the proposed scheme.

A low-complexity time-invariant angle-range dependent directional modulation (DM) based on time-modulated frequency diverse array (TM-FDA-DM) is proposed to achieve point-to-point physical layer security communications. The principle of TM-FDA is elaborated and the vector synthesis method is utilized to realize the proposal, TM-FDA-DM, where normalization and orthogonal matrices are designed to modulate the useful baseband symbols and inserted artificial noise, respectively. Since the two designed matrices are time-invariant fixed values, which avoid real-time calculation, the proposed TM-FDA-DM is much easier to implement than time-invariant DMs based on conventional linear FDA or logarithmical FDA, and it also outperforms the time-invariant angle-range dependent DM that utilizes genetic algorithm (GA) to optimize phase shifters on radio frequency (RF) frontend. Additionally, a robust synthesis method for TM-FDA-DM with imperfect angle and range estimations is proposed by optimizing normalization matrix. Simulations demonstrate that the proposed TM-FDA-DM exhibits time-invariant and angle-range dependent characteristics, and the proposed robust TM-FDA-DM can achieve better BER performance than the non-robust method when the maximum range error is larger than 7km and the maximum angle error is larger than 4°.

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.

For an odd prime q and an integer m≤q, we can construct a regular quasi-cyclic parity-check matrix HI(m,q) that specifies a linear block code CI(m,q), called an improper array code. In this letter, we prove the minimum distance of CI(4,q) is equal to 10 for any q≥11. In addition, we prove the minimum distance of CI(5,q) is upper bounded by 12 for any q≥11 and conjecture the upper bound is tight.