For an uncertain discrete event system (DES) modeled as a set of some possible nondeterministic automata, we address robust supervisory control problems. Based on language models, this paper presents the existence conditions of a robust nonblocking (RN) supervisor that guarantees the absence of blocked states in a closed-loop system. We show that an RN supervisor achieves both a given language specification and the nonblocking characteristics of any nondeterministic automata of the set.

This letter presents parallel algorithms for matrix multiplication and the fast Fourier transform (FFT) that are significant problems arising in engineering and scientific applications. The proposed algorithms are designed on a 3-dimensional processor array with separable buses (PASb). We show that a PASb consisting of N N h processors can compute matrix multiplication of size N N and the FFT of size N in O(N/h+log N) time, respectively. In order to examine ease of hardware implementation, we also evaluate the VLSI complexity of the algorithms. A result obtained achieves an optimal bound on area-time complexity when h=O(N/log N).

In this letter, we propose a two-stage object-based error-concealment technique for MPEG-2 video transmitted in a burst-packet-loss environment. A burst packet loss typically destroys a large area of MPEG-2 coded video. In the first stage, the missing area is intra-picture estimated and concealed in terms of a region-based approach. In the second stage, irregular-moving objects with respect to the background are identified and compensated from the predictive picture. As compared with conventional concealment approaches, the proposed method achieves better PSNR performance and reduces the visual artifacts.

A new graphic and display processor, which is suitable for high-performance car navigation systems or next-generation ITS mobile terminals, has been developed. The performance bottleneck of conventional consumer graphic systems exists not only in the rendering performance of the graphic processor itself, but also in CPU-capability and CPU-bus bandwidth. To release this latter bottleneck, the new processor has Controller/DSP Unit and FPU for graphic-macro-command parsing and geometric operations, respectively, which used to be the CPU tasks and occupy some amount of CPU-bus bandwidth to transfer their results. The architecture of the new processor is organized so as to carry out macro-pipelined operations of graphic and display processing smoothly. One of the features of this processor is having special hardware, Polygon-Engine and Short-Vector-Accelerator, for the rapid rendering of 2D maps, where complex polygons and short line-segments are the dominant objects to be rendered. Another feature is the hardware support of multi-layer/window display with alpha-blend overlapping. This function and additional video processing capability, such as MPEG4 decoding, would be useful in the next generation intelligent terminals. The processor LSI has been successfully fabricated by using 0.18 µm standard CMOS technology. More than five million transistors are implemented on this chip. The peak rendering speed of this processor has been measured as 200 Mpixel/s at 133 MHz processor internal clock frequency. Other results of the graphic system evaluation have demonstrated that this new processor has appropriately high performance and useful functions for the next generation mobile terminals.

In this paper, we present the theoretical analysis of the bit error rate (BER) performance of Single-Carrier Modulation (SCM) and Orthogonal Frequency Division Multiplexing (OFDM) systems under two types of temporally localized man-made noises (generalized shot noise and bursty noise models) environments. The robustness of OFDM system against these two kinds of man-made noises is discussed and then compared with that of SCM system at the same transmission rate. We show that for OFDM system, the BER performance highly depends on the number of subcarriers and the strength of the man-made noise, i.e., the level of the power spectral density of the man-made noise. In addition to the common knowledge on OFDM, we show that OFDM system is sometime less robust to the man-made noises than SCM system.

In loudspeaker-based 3D audio systems, there are some acoustic crosstalk cancellation methods to enlarge the 'sweet spot' around a fixed listener position. However, these methods have common defect that most of them can be applied only to the specific narrow frequency band. In this letter, we propose the more robust acoustic crosstalk cancellation method so that we can cancel the crosstalk signal in far wider frequency band and enlarge 'sweet spot. ' For this goal, we apply a sum and difference filter to the conventional three loudspeaker-based 3D audio system.

Experiments were conducted to examine an approach from language modeling side to improving noisy speech recognition performance. By adopting appropriate word strings as new units of processing, speech recognition performance was improved by acoustic effects as well as by test-set perplexity reduction. Three kinds of word string language models were evaluated, whose additional lexical entries were selected based on combinations of part of speech information, word length, occurrence frequency, and log likelihood ratio of the hypotheses about the bigram frequency. All of the three word string models reduced errors in broadcast news speech recognition, and also lowered test-set perplexity. The word string model based on log likelihood ratio exhibited the best improvement for noisy speech recognition, by which deletion errors were reduced by 26%, substitution errors by 9.3%, and insertion errors by 13%, in the experiments using the speaker-dependent, noise-adapted triphone. Effectiveness of word string models on error reduction was more prominent for noisy speech than for studio-clean speech.

The technique of the digital watermarking is one of the ways to resolve copyright ownership and verify originality of digital contents (e.g. text documents, audio, still images, video, etc.). In this paper, we obtained global robustness and minimal error through using frame based watermarking and including DC and AC coefficients of DCT transform, which extended conventional watermarking method having local robustness and error through using block based and/or AC coefficients only. As a result, the high robustness and quality of our method were proved by several attacks such as lossy image compression, linear filtering, additive noise, scaling, cropping and so on. Watermarks embedded by our method are survived most of JPEG compressions.

The paper presents a topology-oriented robust algorithm for the incremental construction of line arrangements. In order to achieve a robust implementation, the topological and geometrical computations are strictly separated. The topological part is proved to be reliable without any assumption on the accuracy of the geometrical part. A self-correcting property is introduced to minimize the effect of numerical errors. Computational experiments show how the self-correcting property works, and we also discuss some applications of the algorithm.

This paper describes an innovative, high-speed optical backboard bus composed of an optical star coupler, optical-transmitter modules, optical-receiver modules, and optical multi-mode glass fibers. A highly efficient optical coupling structure with an aspherical lens and a laser diode was designed to achieve a coupling efficiency of 90%, enabling distribution of optical signals at up to 1 Gb/s to 50 function boards. Embedded optical fibers in a printed circuit board were used to achieve precise control of the optical propagation delay times and permit a high packaging density. We developed small laser-diode and photo-diode modules suitable for optical coupling with the embedded fibers. A fabricated prototype optical backboard bus controlled by a controller IC mounted on a function board was able to successfully distribute high-speed optical signals to function boards with a high packaging density.

Watermarking techniques are widely used to protect the secret document. In some valuable literatures, most of them concentrate on the binary data watermarking by using comparisons of an original image and a watermarked image to extract the watermark. In this paper, an efficient watermarking algorithm is presented with two-layer hidden for gray-level image watermarking. In the first layer, the key information is found based on the codebook concept. Then the secret key is further hidden to the watermarked image adopting the encryption consisting of spatial distribution in the second layer. The simulations demonstrate that the watermarking information is perceptually invisible in the watermarked image. Moreover, the gray-level watermark can be extracted by referring key parameters rather than the original image, and the extracting quality is very good.

This paper focuses on the watermarking system using a controlled quantization process. We first present a model of the watermark embedding and extracting processes and carry out their analyses. Then we examine the robustness of the watermarking system against common image processing and clarify the reason why detection errors occur in the watermark extracting process. Based on the result, we improve the watermark extracting process and design robust watermarking systems. The improvement is accomplished using a deconvolution filter and neural network techniques. Numerical experiments using the DCT-based watermarking system show good performance as expected by us.

In this paper, we propose an algorithm to calculate the higher moments of the busy period length of a discrete-time M/G/1 type queue with finite buffer. The queueing model has a level-dependent transition probability matrix. Our algorithm is given as a set of recursive formulas which are derived from the relationship among the generating function matrices of the fundamental period. As an example of our algorithm, we provide an approximate analysis of a HOL (Head Of Line) priority control queue.

In the present GHz-clock high-density LSI, a design of signal lines is getting so critical that the transmission line analysis should be introduced to signal line design. This leads to the complex design of line structure and i/o drivers including impedance matching. Our target is to implement a system-in-package (SiP) for software-defined-radio (SDR). The SiP operates up to 10 GHz, and requires a compact and high-density packaging technology with a simple signal wiring design. In this paper, we propose a new concept of 3-D multilayer-stacked SiP. The new 3-D packaging concept includes (1) design guideline for interconnection lengths, (2) bridging register circuits in LSI chips, (3) flip-chip microbump bonding technology of chips onto system-buildup printed wiring boards (PWB), (4) multilayer-stacked 3-D package of several sets of chips and PWB, and (5) 100-µm-diameter bumps at peripheral region of PWB as vertical via-bump bus lines. A critical interconnect length, in which interconnect wiring is treated as a conventional RC line, is discussed for wiring design. Both wiring lengths in LSI chips and that among chips corresponding to total thickness of vertical bus lines are designed to be shorter than the critical length. The key points of the 3-D package for GHz signal transfer are a delay guarantee due to limitation of line length and separation between local lines in a chip and a bus line among chips.

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.

This paper investigates a device model of the power current used for an LSI/IC. The model is proposed to analyze the power bus noise in digital circuit boards. This model is defined in the frequency domain and constructed with an equivalent internal impedance and an equivalent internal current source. Accordingly, the output current of the model is affected by power bus impedance, such as the capacitance of bypass capacitors and the parasitic inductance of power bus wiring. Therefore, the model is useful for analyzing the effectiveness of bypass capacitors and power bus wiring. The structure of equivalent internal impedance for a simple logic IC, such as 74HCXX, can be represented as an RLC series circuit. These parameters are identified by applying the least square method. To demonstrate the validity of the model, an experimental study was conducted. As a result, it was shown that the output current of the model corresponds to the measured current under a variety of power bus impedance levels within 6 dB.

External pins for tests are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip.

Successful e-commerce presupposes techniques by which autonomous trading entities can interoperate. Although progress has been made on data exchange and payment protocols, interoperation in the face of autonomy is still inadequately understood. Current techniques, designed for closed environments, support only the simplest interactions. We develop a multiagent approach for interoperation of business process in e-commerce. This approach consists of (1) a behavioral model to specify autonomous, heterogeneous agents representing different trading entities (businesses, consumers, brokers), (2) a metamodel that provides a language (based on XML) for specifying a variety of service agreements and accommodating exceptions and revisions, and (3) an execution architecture that supports persistent and dynamic (re)execution.

This paper proposes a receding horizon control scheme for a set of uncertain discrete-time linear systems with randomly jumping parameters described by a finite-state Markov process whose jumping transition probabilities are assumed to belong to some convex sets. The control scheme for the underlying systems is based on the minimization of an upper bound on the worst-case infinite horizon cost function at each time instant. It is shown that the mean square stability of the proposed control system is guaranteed under some matrix inequality conditions on the terminal weighting matrices. The proposed controller is obtained using semidefinite programming.

New equivalent characterizations are derived for Schur stability property of real polynomials. They involve a single scalar parameter, which can be regarded as a freedom incorporated in the given polynomials so long as the stability is concerned. Possible applications of the expressions are suggested to the latest results for stability robustness analysis in parameter space. Further, an extension of the characterizations is made to the matrix case, yielding one-parameter expressions of Schur matrices.