The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.

Circuit performance of SiC-MOSFET-based bidirectional isolated DC/DC converters is investigated based on circuit simulation with the physically accurate compact device model HiSIM_HV. It is demonstrated that the combined optimization of the MOSFETs Ron and of the inductances in the transformer can enable a conversion efficiency of more than 97%. The simulation study also verifies that the possible efficiency improvements are diminished due to the MOSFET-performance degradation, namely the carrier-mobility reduction, which results in a limitation of the possible Ron reduction. It is further demonstrated that an optimization of the MOSFET-operation conditions is important to utilize the resulting higher MOSFET performance for achieving additional converter efficiency improvements.

In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si1-xGex virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si1-xGex virtual substrate. The model is found to tally well with the device simulator.

We have improved a compact model for the injection-enhancedinsulated-gate bipolar transistor for inverter circuit simulation. The holeaccumulation of floating-base region and potential change are modeled. It turned out that negative capacitance which occurs by floating-base region has the dependence of frequency. It is necessary to consider the frequency dependence of the total gate capacitance for transient simulation. We analyzed the relationship between negative gate capacitance and current rise rate at the switch turn-on timing and device structure. The development model simulation result is well reproduced $I_{ extrm{c}}$ and $V_{ extrm{ce}}$ of measurement data, and the switching loss calculation accuracy is improved.

The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

In LDMOS devices for high-voltage applications, there appears a notable fingerprint of current-voltage characteristics known as soft breakdown. Its mechanism is analyzed and modeled on LDMOS devices where a high resistive drift region exists. This analysis has revealed that the softness of breakdown, known as the expansion effect, withholding a run-away of current, is contributed by the flux of holes underneath the gate-overlap region originated by impact-ionization. The mechanism of the expansion effect is modeled and implemented into the compact model HiSIM_HV for circuit simulation. A good agreement between simulated characteristics and 2D-device simulation results is verified.

Reverse-recovery modeling for p-i-n diodes in the high current-density conditions are discussed. With the dynamic carrier-distribution-based modeling approach, the reverse recovery behaviors are explained in the high current-density conditions, where the nonquasi-static (NQS) behavior of carriers in the drift region is considered. In addition, a specific feature under the high current-density condition is discussed. The proposed model is implemented into a commercial circuit simulator in the Verilog-A language and its reverse recovery modeling ability is verified with a two-dimensional (2D) device simulator, in comparison to the conventional lumped-charge modeling technique.

The long-standing problem of predicting circuit performance variations without a huge number of statistical investigations is demonstrated to be solvable by a surface-potential-based MOSFET model. Direct connection of model parameters to physical device parameters reflecting process variations and the reduced number of model parameters are the enabling key model properties. It has been proven that the surface-potential-based model HiSIM2 is capable of reproducing measured I-V and its derivatives' variations with those of device/process related model parameters. When used to predict 51-stage ring oscillator frequency variation including both inter- and intra-chip variation, it reproduces measurements with shortened simulation time.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.

Halo doping profile is used in nanoscale surrounding-gate MOSFETs to suppress short channel effect and improve current driving capability. Analytical surface potential and threshold voltage models are derived based on the analytical solution of Poisson's equation for the fully depleted symmetric and asymmetric halo-doped MOSFETs. The validity of the analytical models is verified using 3D numerical simulation. The performance of the halo-doped MOSFETs are studied and compared with the uniformly doped surrounding-gate MOSFETs. It is shown that the halo-doped channel can suppress threshold voltage roll-off and drain-induced barrier lowering, and improve carrier transport efficiency. The asymmetric halo structure is better in suppressing hot carrier effect than the symmetric halo structure.

An overview on the physics and circuit design oriented background of the advanced compact model HICUM is presented. Related topics such as the approach employed for geometry scaling and parameter extraction are briefly discussed. A model hierarchy is introduced, that addresses a variety of requirements encountered during the increasingly complicated task of designing analog and high-frequency circuits.

We present measurements of Gate-Induced-Drain-Leak-age at various temperatures and terminal biases. Besides Band-to-Band tunneling leakage observed at high Drain-to-Gate voltage VDG, we also observed Trap-Assisted-Tunneling leakage current at lower VDG. Based on ISE TCAD simulations of the electric field, we propose analytical models for Band-to-Band and Trap-Assisted Gate-Induced-Drain-Leakage currents suitable for compact modeling.

The new design with minimum loop inductance suitable for the measurements at high frequencies with substrate bias is described. These test structures allow characterizing 4-terminal MOSFETs with a standard two-port Network Analyzer. The high-frequency behavior of bulk effect in MOSFETs is studied at different bias conditions for a 0.18 µm RF CMOS technology. The BSIM3 extension RF MOSFET modeling with bulk effect is verified and analyzed from two-port Y-parameter results. The result of RF NMOSFET shows that a good accuracy of the 4-terminal RF MOSFET modeling is achieved.

The rapid down-scaling of minimum feature size in CMOS technologies has boosted the RF performance, thereby opening up the RF application area to CMOS. The concurrent reduction of supply voltage pushes the MOSFETs used in circuit design more and more into the moderate-inversion regime of operation. As a consequence, compact MOS models are needed that are accurate in all operating regimes, including the moderate-inversion regime. Advanced analogue applications require accurate modelling of distortion, capacitances and noise. RF application of MOSFETs require the extension of this accurate modelling up to high frequencies and in addition accurate modelling of impedance levels and power gain. The implications for compact MOS models will be discussed, together with the state-of-the-art in compact MOS modelling. Special attention will be paid to some well-known circuit examples, and the compact model requirements needed for a correct description. Where relevant MOS Model 11 will be used to illustrate the discussion.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

Physical models for fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs are overviewed, and recent applications of them (in SOISPICE) are described, stressing the need for good physics-based accounting for the inherently coupled bipolar and MOS device features in reliable circuit design. The applications suggest that asymmetrical double-gate FD/SOI CMOS technology can be scaled below 0.1 µm, whereas the single-gate counterpart seemingly cannot be, and that the floating-body charge dynamics and the associated transient leakage current in NFD/SOI (and FD/SOI) pass transistors in memory (DRAM and SRAM) circuits can be effectively controlled by optimal device design.

This work deals with thermal-noise modeling for silicon vertical bipolar junction transistors (BJTs) and relevant integrated circuits (ICs) operating at low currents. The two-junction BJT compact model is consistently derived from the thermal-noise generalization of the Shockley semiconductor equations developed in work which treats thermal noise as the noise associated with carrier velocity fluctuations. This model describes BJT with the Itô non-linear stochastic-differential-equation (SDE) system and is suitable for large-signal large-fluctuation analysis. It is shown that thermal noise in silicon p-n-junction diode contributes to "microplasma" noise. The above model opens way for a consistent-modeling-based design/optimization of bipolar device noise performance with the help of theory of Itô's SDEs.