Short-time withstand current is one of the crucial nominal parameters in air circuit breaker. A numerical method to evaluate the short-time withstand current is proposed. Cylindrical current carrying bridge is introduced to describe the contact spot between movable and fixed contacts. Taking into account the action of ferromagnetic splitter plates, the variation of the conductor properties with temperature and the variation of contact spot radius with the electro-dynamic repulsion force, a transient finite element calculation model is developed by coupling the electromagnetic field and thermal field. The loaded short circuit current is considered as the short-time withstand current once the highest temperature is near to the melting point of the contact material. It demonstrates that the method is useful to evaluate the performance of the air circuit breaker.

The mechanism of current collapse of AlGaN/GaN heterojunction field-effect transistors (HFETs) was investigated by gate bias stress with and without illumination. It is clarified that there are two positions where negative charges accumulate, at the gate edge and in the bulk epi-layer. In the gate-edge mode, the charge comes either through the passivation film or the AlGaN layer, depending on the resistance of the films. Reduction of leakage current in the passivation film will be important to suppress the surface-related collapse.

To reduce the gate leakage current of AlGaN/GaN HEMTs, we selected ITO/Ni/Au for Schottky electrodes and Schottky characteristics were compared with those of Ni/Au electrodes. ITO/Ni/Au and Ni/Au electrodes were deposited by vacuum evaporation and annealed at 350 in nitrogen atmosphere. From the I-V evaluation results of ITO/Ni/Au electrodes, forward and reverse leakage currents were reduced. Schottky characteristics of ITO/Ni/Au electrodes were also improved compared to these of Ni/Au electrodes. In addition, substantial decrease of leakage currents was confirmed after the annealing of HEMTs with ITO/Ni/Au electrodes. This may be explained that ITO/AlGaN interface state became lower by the annealing. By the temperature dependence of I-V curves, clear dependence was confirmed for the gates with ITO/Ni/Au electrodes. On the other hand, small dependence was observed for those with Ni/Au electrodes. From these results, tunnel leakage currents were dominant for the gates with Ni/Au electrode. Thermal emission current was dominant for the gates with ITO/Ni/Au electrode. The larger temperature dependence was caused that ITO/AlGaN interface states were smaller than those for Ni/Au electrode. It was suggested that suppressed AlGaN Schottky barrier thinning was caused by the surface defect donors, then tunneling leakage currents were decreased. We evaluated HEMT characteristics with ITO/Ni/Au electrode and Ni/Au electrode. Id max and Gm max were similar characteristics, but Vth with ITO/Ni/Au electrode was shifted +0.4 V than that with Ni/Au electrode due to the higher Schottky barrier. It was confirmed to have a good pinch-off currents and low gate leakage currents by ITO/Ni/Au electrodes.

In AlGaN/GaN high electron mobility transistors (HEMTs), drain current reduction by current collapse phenomenon is a big obstacle for a high efficient operation of power amplifier application. In this study, we investigated the effects of SiN passivation film quality on the electrical characteristics of AlGaN/GaN HEMTs. First, we conducted some experiments to investigate the relationship between electrical characteristics of AlGaN/GaN HEMTs and various conditions of SiN passivation film by plasma enhanced chemical vapor deposition (PE-CVD). We found that both gate current leakage and current collapse were improved simultaneously by SiN passivation film deposited by optimized condition of NH3 and SiH4 gas flow. It is found that the critical parameter in the optimization is a IN-H/ ISi-H ratio measured by Fourier transforms infrared spectroscopy (FT-IR) spectra. Next, a thermal CVD SiN was applied to the passivation film to be investigated from the same point of view, because a thermal CVD SiN is well known to have good quality with low hydrogen content and high IN-H/ISi-H ratio. We confirmed that the thermal CVD SiN passivation could improve much further both of the gate leakage current and the current collapse in AlGaN/GaN-HEMTs. Furthermore, we tried to apply the thermal CVD SiN to the gate insulator in MIS (Metal Insulator Semiconductor) structure of AlGaN/GaN HEMTs. The thermal CVD SiN passivation was more suitable for the gate insulator than PE-CVD SiN passivation in a view of reducing current collapse phenomena. It could be believed that the thermal CVD SiN film is superior to the PE-CVD SiN film to achieve good passivation and gate insulator film for AlGaN/GaN HEMTs due to the low hydrogen content and the high IN-H/ISi-H ratio.

PIN diodes for digital X-ray detection as a single photon counting sensor were fabricated on a floating-zone (FZ) n-type (111), high resistivity (5-10 kΩcm) silicon substrates (500 µm thickness). Its electrical properties such as the leakage current and the breakdown voltage were characterized. The size of pixels was 100 µm100 µm. The p+ guard-ring was formed around the active area to reduce the leakage current. After the p+ active area and guard-ring were fabricated by the ion-implantation, the extrinsic-gettering on the wafer backside was performed to reduce the leakage current by n+ ion-implantation. PECVD oxide was deposited as an IMD layer on front side and then, metal lines were formed on both sides of wafers. The leakage current of detectors was significantly reduced with a guard-ring when compared with that without a guard ring. The leakage current showed the strong dependency on the gap distance between the active area and the guard ring. It was possible to achieve the leakage current lower than 0.2 nA/cm2.

Despite the extensive literature on current conveyor-based universal (namely, low-pass, band-pass, high-pass, notch, and all-pass) biquads with three inputs and one output, no filter circuits have been reported to date which simultaneously achieve the following seven important features: (i) employment of only two current conveyors, (ii) employment of only grounded capacitors, (iii) employment of only grounded resistors, (iv) high-input and low-output impedance, (v) no need to employ inverting type input signals, (vi) no need to impose component choice conditions to realize specific filtering functions, and (vii) low active and passive sensitivity performances. This letter describes a new voltage-mode biquad circuit that satisfies all the above features simultaneously, and without trade-offs.

Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for 40% or more of the total energy consumed in these systems. Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Moreover, temperature is another factor that exponentially increases the leakage current. In this paper, we show the effect of temperature on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. Our results show that for a given application and technology, the optimal cache size moves toward smaller caches at higher temperatures, due to the larger leakage. Consequently, a Temperature-Aware Configurable Cache (TACC) is an effective way to save energy in finer technologies when the embedded system is used in different temperatures. Our results show that using a TACC, up to 61% energy can be saved for instruction cache and 77% for data cache compared to a configurable cache that has been configured for only the corner-case temperature (100). Furthermore, the TACC also enhances the performance by up to 28% for the instruction cache and up to 17% for the data cache.

For a globally asynchronous locally synchronous (GALS) system, data transfer mechanisms based on a current-mode multiple valued logic (CMMVL) has been studied to reduce complexity and power dissipation of wires. However, these schemes consume considerable amount of power even in idle states because of the static power caused by their inherent structure. In this paper, new encoder and decoder circuits using CMMVL are suggested to reduce the static power. The effectiveness of the proposed data transfer is validated by comparisons with the previous CMMVL scheme and conventional voltage-mode schemes such as dual-rail and 1-of-4 encodings through simulation with a 0.25-µm CMOS technology. Simulation results demonstrate that the proposed CMMVL scheme significantly reduces power consumption of the previous one and is superior to dual-rail and 1-of-4 schemes over wire length of 2 mm and 4 mm, respectively.

This paper presents a design of an asynchronous peer-to-peer half-duplex/full-duplex-selectable data-transfer system on-chip interconnected. The data-transfer method between channels is based on a 1-phase signaling scheme realized by using multiple-valued current-mode (MVCM) circuits and encoding, which performs high-speed communication. A data transmission is selectable by adding a mode-detection circuit that observes data-transmission modes; full-duplex, half-duplex and standby modes. Especially, since current sources are completely cut off during the standby mode, the power dissipation can be greatly reduced. Moreover, both half-duplex and full-duplex communication can be realized by sharing a common circuit except a signal-level conversion circuit. The proposed interface is implemented using 0.18-µm CMOS, and its performance improvement is discussed in comparison with those of the other ordinary asynchronous methods.

This paper proposes an efficient systolic array construction method for optimal planar systolic design of the matrix multiplication. By connection network adjustment among systolic array processing element (PE), the input/output data are jumping in the systolic array for multiplication operation requirements. Various 2-D systolic array topologies, such as square topology and hexagonal topology, have been studied to construct appropriate systolic array configuration and realize high performance matrix multiplication. Based on traditional Kung-Leiserson systolic architecture, the proposed "Jumping Systolic Array (JSA)" algorithm can increase the matrix multiplication speed with less processing elements and few data registers attachment. New systolic arrays, such as square jumping array, redundant dummy latency jumping hexagonal array, and compact parallel flow jumping hexagonal array, are also proposed to improve the concurrent system operation efficiency. Experimental results prove that the JSA algorithm can realize fully concurrent operation and dominate other systolic architectures in the specific systolic array system characteristics, such as band width, matrix complexity, or expansion capability.

This work presents an ultra-low-voltage ultra-low-power weak inversion composite MOS transistor. The steady state power consumption and the linear swing signal of the composite transistor are comparable to a single transistor, whereas presenting very high output impedance. This work also presents two interesting applications for the composite transistor; a 1:1 current mirror and an extremely low power temperature sensor, a thermistor. Both implementations are verified in a standard 0.35-µm TSMC CMOS process. The current mirror presents high output impedance, comparable to the cascode configuration, which is highly desirable to improve gain and PSRR of amplifiers circuits, and mirroring relation in current mirrors.

A current-mode squarer/divider circuit with a novel translinear cell is presented for automotive applications. The proposed circuit technique increases the accuracy of the squarer/divider function with better input dynamic range and temperature insensitivity. Simulation results show that the variation of the output current is within ±0.2% over the temperature range from -40 to 140.

This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35 µm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70 mW at 3.3 V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.

The call-level performance modelling is a challenge in the highly heterogeneous environment of modern telecom networks, due to the presence of elastic traffic. In this paper, we review existing teletraffic loss models and propose a model for elastic traffic of service-classes with finite population (quasi-random call arrival process). Upon arrival, calls have contingency alternative bandwidth requirements that depend on thresholds which indicate the available/occupied link bandwidth (state dependent model). Calls are admitted under the complete sharing policy, and can tolerate bandwidth compression, while in-service. We prove a recurrent formula for the efficient calculation of the link occupancy distribution and consequently the call blocking probabilities and link utilization. The accuracy of the proposed model is verified by simulation and is found to be quite satisfactory. Comparative results with other existing models show the necessity and the effectiveness of the proposed model. Its potential applications are mainly in the environment of wireless networks.

This letter presents a low-power switched current (SI) memory cell with CMOS-type configuration. By combining nMOS and pMOS in the SI memory cell and using a polarity discrimination circuit, we design a CMOS-type SI memory cell which eliminates the quiescent current in the SI memory cell. The simulation result shows that the CMOS-type SI memory cell consumes less power than the conventional class-AB memory cell.

A concurrent model of computation and a language based on the model for bit-level operation are useful for developing asynchronous and concurrent programs compositionally, which frequently use bit-level operations. Some examples are programs for video games, hardware emulation (including virtual machines), and signal processing. However, few models and languages are optimized and oriented to bit-level concurrent computation. We previously developed a visual programming language called A-BITS for bit-level concurrent programming. The language is based on a dataflow-like model that computes using processes that provide serial bit-level operations and FIFO buffers connected to them. It can express bit-level computation naturally and develop compositionally. We then devised a concurrent computation model called APEC (Asynchronous Program Elements Connection) for bit-level concurrent computation. This model enables precise and formal expression of the process of computation, and a notion of primitive program elements for controlling and operating can be expressed synthetically. Specifically, the model is based on a notion of uniform primitive processes, called primitives, that have three terminals and four ordered rules at most, as well as on bidirectional communication using vehicles called carriers. A new notion is that a carrier moving between two terminals can briefly express some kinds of computation such as synchronization and bidirectional communication. The model's properties make it most applicable to bit-level computation compositionally, since the uniform computation elements are enough to develop components that have practical functionality. Through future application of the model, our research may enable further research on a base model of fine-grain parallel computer architecture, since the model is suitable for expressing massive concurrency by a network of primitives.

This paper proposes a method (Group-Linking Method) that has control over the complexity of the sequential function to construct Finite Memory Machines with minimal order--the machines have the largest number of states based on their memory taps. Finding a machine with maximum number of states is a nontrivial problem because the total number of machines with memory order k is (256)2k-2, a pretty large number. Based on the analysis of Group-Linking Method, it is shown that the amount of data necessary to reconstruct an FMM is the set of strings not longer than the depth of the machine plus one, which is significantly less than that required for traditional greedy-based machine learning algorithm. Group-Linking Method provides a useful systematic way of generating unified benchmarks to evaluate the capability of machine learning techniques. One example is to test the learning capability of recurrent neural networks. The problem of encoding finite state machines with recurrent neural networks has been extensively explored. However, the great representation power of those networks does not guarantee the solution in terms of learning exists. Previous learning benchmarks are shown to be not rich enough structurally in term of solutions in weight space. This set of benchmarks with great expressive power can serve as a convenient framework in which to study the learning and computation capabilities of various network models. A fundamental understanding of the capabilities of these networks will allow users to be able to select the most appropriate model for a given application.

Because the leakage current of a digital circuit depends on the states of the circuit's logic gates, assigning a minimum leakage vector (MLV) for the primary inputs and the flip-flops' outputs of the circuit that operates in the sleep mode is a popular technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike most traditional techniques that ignore the leakage current overhead of the newborn vector controller, our technique can take this overhead into account. Ignoring this overhead during solution space exploration may bring a side effect that is misrecognizing a non-optimal solution as an optimal one. Experimental results show that our heuristic algorithm can reduce the leakage current up to 59.5% and can find the optimal solutions on most of the small MCNC benchmark circuits. Moreover, the required CPU time of our probability-based program is significantly less than that of a random search program.

Recently, technology roadmaps have been actively constructed by various organizations such as governments, industry segments, academic societies and companies [1]. While the common basic purpose of these roadmaps is sharing common recognition of the technology among stakeholders, there exists a specific role for each organization. One of the important roles of academic societies is to show the directions in which society is moving. The IEICE technical group on Concurrent System Technology (CST) established in 1993 stands at a turning point and needs to move forward in new directions after more than a decade of activities and contributions. However, neither top-down (market-pull/requirements-pull) nor bottom-up (technology-push) roadmapping is suitable for CST because CST is a kind of systems engineering. This paper proposes a new technology roadmapping methodology (middle-up-down technology roadmapping) for systems engineering and shows three future directions of CST and one roadmap for service systems that integrate CST and services science.

A novel driving concept, "pulse-width modulation with current uniformization," is proposed for thin-film transistor driven organic light-emitting diode displays (TFT-OLEDs). An example of this driving concept is the combination of "pulse-width modulation with a self-biased inverter" and a "time-ratio grayscale with current uniformization." Its driving operation is confirmed by circuit simulation. It is found that this driving method can compensate the characteristic deviations and degradations of both TFTs and OLEDs and immensely improve luminance uniformity. Finally, its driving operation is also confirmed by an actual pixel equivalent circuit.