In this letter, we describe a low power current to time converter for wireless sensor networks. The proposed circuit has some advantages of high linearity and wide measurement range. From the evaluation using HSPICE with 0.18 µm CMOS device parameters, the output differential error for the input current variation is approximately 0.1 µs/nA under the condition that the current is varied from 100 nA to 500 nA. The idle power consumption is approximately zero.

This paper presents a possibility of Electromagnetic (EM) analysis against cryptographic modules outside their security boundaries. The mechanism behind the information leakage is explained from the view point of Electromagnetic Compatibility: electric fluctuation released from cryptographic modules can conduct to peripheral circuits based on ground bounce, resulting in radiation. We demonstrate the consequence of the mechanism through experiments where the ISO/IEC standard block cipher AES (Advanced Encryption Standard) is implemented on an FPGA board and EM radiations from power and communication cables are measured. Correlation Electromagnetic Analysis (CEMA) is conducted in order to evaluate the information leakage. The experimental results show that secret keys are revealed even though there are various disturbing factors such as voltage regulators and AC/DC converters between the target module and the measurement points. We also discuss information-suppression techniques as electrical-level countermeasures against such CEMAs.

We have developed a long-range asynchronous on-chip data-transmission link based on multiple-valued single-track signaling for a highly reliable asynchronous Network-on-Chip. In the proposed signaling, 1-bit data with control information is represented by using a one-digit multi-level signal, so serial data can be transmitted asynchronously using only a single wire. The small number of wires alleviates the routing complexity of wiring long-range interconnects. The use of current-mode signaling makes it possible to transmit data at high speed without buffers or repeaters over a long interconnect wire because of the low-voltage swing of signaling, and it leads to low-latency data transmission. We achieve a latency of 0.45 ns, a throughput of 1.25 Gbps, and energy dissipation of 0.58 pJ/bit with a 10-mm interconnect wire under a 0.13 µm CMOS technology. This represents an 85% decrease in latency, a 150% increase in throughput, and a 90% decrease in energy dissipation compared to a conventional serial asynchronous data-transmission link.

A sub-mW current-reuse CMOS VCO is presented for wireless sensor network applications. In order to break the interdependence between the current consumption and the phase noise performance in the conventional current-reuse structure, a tail current source is added to the switching core in such a way that they are simultaneously switched during operation. With this, the current consumption can be maintained at a minimum level while the FET size can be optimally determined for large swing and good phase noise performances. The proposed VCO's advantage of achieving low phase noise at low current consumption is clearly demonstrated by simulations in comparison to the conventional structure. The proposed VCO is implemented in 0.13 µm CMOS. It dissipates 0.6 mW from 1.2 V supply. The measured phase noise at the output frequency of 2.28 GHz is -121 dBc/Hz at 1 MHz offset.

Effects of conductive defects on unipolar resistive random access memory (RRAM) are investigated in order to reduce the operation current for high density and low power RRAM applications. It is clarified that forming voltage decreases with increasing charged conductive defects which are a source of conductive filament (CF) path and with decreasing cell thickness. Random circuit breaker (RCB) network simulation model which is a dynamic percolation simulation model is used to elucidate these effects. From this simulation results, the optimal cell thickness with sufficient conductive defect shows improved resistive switching characteristics such as low forming voltage, small set voltage distribution and low reset current. From the deep understanding of relationship between conductive defect in various cell thickness and other resistive switching parameters, RRAM with low forming voltage and reset current can be obtained and it will be one of the most promising next generation nonvolatile memories.

In this paper, a Schmitt Trigger based 10T SRAM (ST 10T SRAM) cell with the vertical MOSFET is proposed for low supply voltage operation, and its impacts on cell size, stability and speed performance are investigated. The proposed ST 10T SRAM cell with the vertical MOSFET achieves smaller cell size than the ST 10T SRAM cell with the conventional planar MOSFET. Moreover, the proposed SRAM cell realizes large and constant static noise margin (SNM) against bottom node resistance of the vertical MOSFET without any architectural changes from the present 6T SRAM architecture. The proposed SRAM cell also suppresses the degradation of the read time of the ST 10T SRAM cell due to the back-bias effect free characteristic of the vertical MOSFET. The proposed ST 10T SRAM cell with the vertical MOSFET is a superior SRAM cell for low supply voltage operation with a small cell size, stable operation, and fast speed performance with the present 6T SRAM architecture.

In this paper, a theoretical analysis of current-controlled (CC-) MOS current mode logic (MCML) is reported. Furthermore, the circuit performance of the CC-MCML with the auto-detection of threshold voltage (Vth) fluctuation is evaluated. The proposed CC-MCML with the auto-detection of Vth fluctuation automatically suppresses the degradation of circuit performance induced by the Vth fluctuations of the transistors automatically, by detecting these fluctuations. When a Vth fluctuation of ± 0.1 V occurs on the circuit, the cutoff frequency of the circuit is increased from 0 Hz to 3.5 GHz by using the proposed CC-MCML with the auto-detection of Vth fluctuation.

Current sources are essential components for analog circuit designs, the mismatch of which causes the significant degradation of the circuit performance. This paper addresses the mismatch model of CMOS current sources, unlike the conventional modeling, focusing on the layout- and λ-dependency of the process variation, where λ is the output conductance parameter. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90 nm process technology, where we can collect the characteristics variation data for MOSFETs of various layouts. The test chip also includes D/A converters to check the differential non-linearity (DNL) caused by the mismatch of current sources when behaving as a DAC. Identifying the variation and the circuit-level errors in the measured DNLs, we reveal that our model can more accurately account for the current variation compared to the conventional mismatch model.

By using a quadratic compensation slope, a CMOS current-mode buck DC-DC converter with constant frequency characteristics over wide input and output voltage ranges has been developed. The use of a quadratic slope instead of a conventional linear slope makes both the damping factor in the transfer function and the frequency bandwidth of the current feedback loop independent of the converter's output voltage settings. When the coefficient of the quadratic slope is chosen to be dependent on the input voltage settings, the damping factor in the transfer function and the frequency bandwidth of the current feedback loop both become independent of the input voltage settings. Thus, both the input and output voltage dependences in the current feedback loop are eliminated, the frequency characteristics become constant, and the frequency bandwidth is maximized. To verify the effectiveness of a quadratic compensation slope with a coefficient that is dependent on the input voltage in a buck DC-DC converter, we fabricated a test chip using a 0.18 µm high-voltage CMOS process. The evaluation results show that the frequency characteristics of both the total feedback loop and the current feedback loop are constant even when the input and output voltages are changed from 2.5 V to 7 V and from 0.5 V to 5.6 V, respectively, using a 3 MHz clock.

This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

In this paper, a decentralized concurrent transmission strategy in shared channel in Ad Hoc networks is proposed based on game theory. Firstly, a static concurrent transmissions game is used to determine the candidates for transmitting by channel quality threshold and to maximize the overall throughput with consideration of channel quality variation. To achieve NES (Nash Equilibrium Solution), the selfish behaviors of node to attempt to improve the channel gain unilaterally are evaluated. Therefore, this game allows each node to be distributed and to decide whether to transmit concurrently with others or not depending on NES. Secondly, as there are always some nodes with lower channel gain than NES, which are defined as hunger nodes in this paper, a hunger suppression scheme is proposed by adjusting the price function with interferences reservation and forward relay, to fairly give hunger nodes transmission opportunities. Finally, inspired by stock trading, a dynamic concurrent transmission threshold determination scheme is implemented to make the static game practical. Numerical results show that the proposed scheme is feasible to increase concurrent transmission opportunities for active nodes, and at the same time, the number of hunger nodes is greatly reduced with the least increase of threshold by interferences reservation. Also, the good performance on network goodput of the proposed model can be seen from the results.

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for 2-dimensional microbolometer infrared focal plane arrays (IRFPAs). The integration time and signal-to-noise ratio (SNR) is improved using the current-mode bias and MSB skimming. The proposed pixel-level ADC is a two-step configuration, so its power consumption is very low. The readout circuit was designed using a 0.35 µm 2-poly 4-metal CMOS process for a 320240 microbolometer array with a pixel size of 35µm35µm. The noise equivalent temperature difference (NETD) was estimated to be 47 mK, with a power consumption of 390 nW for a pixel-level ADC.

Petri net is a powerful modeling tool for concurrent systems. Subclasses of Petri net are suggested to model certain realistic applications with less computational cost. Structurally weakly persistent net (SWPN) is one of such subclasses where liveness is verified in deterministic polynomial time. This paper studies the computational complexity to verify whether a give net is SWPN. 3UNSAT problem is reduced to the problem to verify whether a net is not SWPN. This implies co-NP completeness of verification problem of SWPN.

When contact failure occurs in a connector in a coaxial high-frequency (HF) signal transmission line, it is well known that common-mode (CM) radiation occurs on the line. We focus on contact conditions in a connector causing such CM radiation. Experiments and simulations verify that CM radiation increases as the contact resistance increases. While the CM current strongly depends on the distribution pattern of contact resistances at a low resistance, the CM current does not depend on these pattern at a high resistance. Our results indicate that it is important to maintain a symmetrical distribution of contact spots whenever the number of such spots is four or more.

In order to study the influences of contact opening speeds on arc extinction gap length characteristics, Ag contacts were operated to break DC inductive load currents from 0.1 A to 2.0 A at 14 V with contact opening speeds of 0.5 mm/s, 1 mm/s, 2 mm/s, 5 mm/s and 10 mm/s in a switching mechanism employing a stepping motor, and arc voltage waveforms were observed at each opening of the contacts. From the results, the average arc durations were determined at each current level under the respective contact opening speeds, and the average arc extinction gap lengths were calculated by multiplying the average arc duration value and the contact opening speed value. It was found that average arc durations showed no significant differences with increasing contact opening speeds. Thus, arc extinction gaps became larger at faster opening speeds in the inductive load conditions of this study.

An arc model has been applied in this paper to study the fundamental interruption environment of a 550 kV SF6 single-break tank circuit breaker. The full differential model takes into account of all important physical mechanisms and is implemented into a commercial Computational Fluid Dynamics (CFD) package, PHOENICS. The model takes a magneto-hydro-dynamics (MHD) approach and the governing equations are solved using the Finite Volume Method (FVM). Through the simulation, the flow velocity vector and mach number for capacitive current switching and short-circuit current breaking are analyzed, and flow dynamic characteristics are obtained. The simulation can provide helpful reference for the design of 550 kV SF6 single-break tank circuit breaker.

Recently, for electronic devices operating at high frequencies, the suppression of a high-frequency electromagnetic field of 1 GHz or more has become necessary. We focus on a loose connector between a pair of electrical devices operating in the high-frequency band. Many electronic devices are used in living spaces, most of which are connected to one another. When a user connects two devices, achieving good contact only by finger tightening can be difficult. Accordingly, in this paper, considering the case where the tightening torque of a coaxial connector is insufficient, we analyze the effect of loose contact on electromagnetic field radiation from a transmission line.

In this letter, a novel body bias selection scheme for minimizing the leakage of MOS transistors is presented. The proposed scheme directly monitors leakages at present and adjacent body bias voltages, and dynamically updates the voltage at which the leakage is minimized regardless of process and temperature variations. Comparison results in a 46 nm CMOS technology indicated that the proposed scheme achieved leakage reductions of up to 68% as compared to conventional body biasing schemes.

Using a self-developed ASTM test system of contact material electrical properties under low voltage (LV), small-capacity, the current-frequency variable and a photoelectric analytical balance, the electric performance comparison experiments and material weighing of silver-based electrical contact materials, such as silver/tungsten and silver/cadmium oxide contact materials, are completed under LV, pure resistive load and small current at 400 Hz/50 Hz. The surface profiles and constituents of silver/tungsten contact material were observed and analyzed by SEM and EDAX. Researches indicate that the form of the contact material arc burnout at 400 Hz is stasis, not an eddy flow style at 50 Hz; meanwhile, the area of the contact burnout at 400 Hz is less than that of 50 Hz, and the local ablation on the surface layer at 400 Hz is more serious. Comparing the capacities of the silver-based contact materials with different second element such as CAgW50, CAgNi10, CAgC4 and CAgCdO15 at 400 Hz, no matter what the performances of arc erosion resistance or welding resistance, it can be found that the capacities of the silver/tungsten material is the best.

With measuring the arc current, arc voltage and arc images, the high-current air arc commutation process across the separated electrodes was investigated. It shows that the existence of a short stable arc in the gap may increase the current commutation time. According to the energy balance of the arc column, the conditions to maintain the short stable arc were introduced and the effects of the current limiting resistance on the current commutation process were discussed.