This paper presents a current-reused quadrature voltage-controlled oscillator (QVCO) which adopts a source-connection coupling structure. The QVCO simultaneously achieves low phase noise and low power consumption by newly combining current-reused VCOs and coupling transistors. The measured QVCO obtains good FoM of -188.2 dBc at a frequency of 2.2 GHz with 3.96 mW power consumption.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

We achieve concurrent access to WiFi and WiMAX networks on a mobile terminal equipped with a common RF subsystem by providing time-interleaved RF access control schemes to both of the MAC layers. We propose cooperative and competitive sharing schemes, neither of which requires any modification to other network components. We implement our schemes on a WiFi/WiMAX dual-mode SoC platform. Experimental results show that these schemes work and have affordable overheads.

Progress of roles and schemes of calibration techniques in data converters are reviewed. Correction techniques of matching error and nonlinearity in analog circuits have been developed by digital assist using high-density and low-power digital circuits. The roles of the calibration are not only to improve accuracy but also to reduce power dissipation and chip area. Among various calibration schemes, the background calibration has significant advantages to achieve robustness to fast ambient change. Firstly the nonlinearity calibrations for pipeline ADCs are reviewed. They have required new solutions for redundancy of the circuits, an error estimation algorithm and reference signals. Currently utilizing the calibration techniques, the performance of 100 Msps and 12 bit has been achieved with 10 mW power dissipation. Secondly the background calibrations of matching error in flash ADC and DAC with error feedback to the analog circuits are described. The flash ADC utilizes the comparator offset correction with successive approximation algorithm. The DAC adopts a self current matching scheme with an analog memory. Measured dissipation power of the ADC is 0.38 mW at 300 MHz clock. Effects of the background calibration to suppress crosstalk noise are also discussed.

In order to realize Integrated Circuits (IC) with operation over the 10 GHz range, conventional CMOS logic faces critical issues, such as increasing power consumption, and difficulty to aggressively scale the device size and so on. To overcome this issue, we have proposed Current Controlled-MOS Current Mode Logic (CC-MCML) to realize the reduction of power consumption and the enhancement of the operation speed in logic circuits without scaling the gate length of the MOSFET, and confirmed the performance of these circuits both theoretically and experimentally. In the CC-MCML it is extremely important to control the input voltage of the MOSFET used as the constant current source in order to make the base voltage of the input signal and the output signal equivalent. In this paper, we propose CC-MCML/MTJ (Magnetic Tunnel Junction) circuit, which is one type of nonvolatile memory hybrid circuit technology. A more stable and precise operation is realized by cutting the range of the input voltage of the constant current source, and it is shown that the operation of CC-MCML/MTJ Hybrid Circuit enables us to suppress the base voltage difference due to the Vth fluctuation in comparison with the conventional CC-MCML. These results imply the high potential of Si-CMOS/Spintronics Hybrid technologies for future IC.

We have succeeded in fabricating 180 nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180 nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔVB. The ΔVB, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53 V to 0.69 V, and threshold voltage of PMOS fluctuates in the range of -0.47 V to -0.67 V, the CC-MCML technique is able to suppress ΔVB within only 30 mV, where as the conventional MCML technique caused maximum ΔVB of 1.0 V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.

In this paper, a 24 GHz frequency source for low phase noise is presented in a 0.18 µm CMOS process. The 24 GHz frequency source chip is composed of a 12 GHz voltage controlled oscillator (VCO) and a 24 GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12 GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17 dBc/Hz at a 1 MHz offset frequency and -20.95 dB at 23.19 GHz frequency, respectively. The measured frequency tuning range is from 23.19 GHz to 24.76 GHz drawing 2.72 mA at a supply voltage of 1.8 V not including an output buffer.

This paper presents a resistor-compensation technique for a CMOS bandgap and current reference, which utilizes various high positive temperature coefficient (TC) resistors, a two-stage operational transconductance amplifier (OTA) and a simplified start-up circuit in the 0.35-µm CMOS process. In the proposed bandgap and current reference, numerous compensated resistors, which have a high positive temperature coefficient (TC), are added to the parasitic n-p-n and p-n-p bipolar junction transistor devices, to generate a temperature-independent voltage reference and current reference. The measurements verify a current reference of 735.6 nA, the voltage reference of 888.1 mV, and the power consumption of 91.28 µW at a supply voltage of 3.3 V. The voltage TC is 49 ppm/ in the temperature range from 0 to 100 and 12.8 ppm/ from 30 to 100. The current TC is 119.2 ppm/ at temperatures of 0 to 100. Measurement results also demonstrate a stable voltage reference at high temperature (> 30), and a constant current reference at low temperature (< 70).

This paper presents a 7 GHz differential current-reused voltage-controlled oscillator (CR-VCO) with low power consumption and low phase noise using 0.18-µm CMOS technology. The output power of this CR-VCO is enhanced by utilizing a trifilar-transformer-feedback technique. The lower phase noise is achieved by the more symmetric voltage swings resulting from the improved balance of switching current. At a 1.5-V DC supply voltage, the power dissipation is only 3.4 mW. The total tuning range is 1.4 GHz (17.9%) as the tuning voltage ranges from 0 V to 1.8 V. The optimum phase noise is around -117.3 dBc/Hz at a frequency offset of 1 MHz from the center frequency of 7.07 GHz. The corresponding output power is around -6.8 dBm. For the proposed CR-VCO, the calculated figures-of-merit, FOM and FOMT , are -188.9 and -193.9 dBc/Hz, respectively.

On uniformly convex real Banach spaces, a fixed point theorem in weak topology for successively recurrent system of fuzzy-set-valued nonlinear mapping equations and its application to ring nonlinear network systems are theoretically discussed in detail. An arbitrarily-level likelihood signal estimation is then established.

Dicode partial response signaling system over inductively-coupled channel has been developed to achieve higher data rate than self-resonant frequencies of inductors. The developed system operates at five times higher data rates than conventional systems with the same inductor. A current-mode equalization in the transmitter designed in a 90-nm CMOS successfully reshapes waveforms to obtain dicode signals at the receiver. For a 5-Gb/s signaling through the coupled inductors with a 120-µm diameter and a 120-µm distance, 20-mV eye opening was observed. The power consumption value of the transmitter was 58 mW at the 5-Gb/s operation.

Although larger scale integration enhances the practicability of superconducting Josephson circuits, several technical problems begin to emerge during its progress. One of the problems is the increase of current through a ground plane (ground current). Excess ground current produces additional magnetic field and reduces operation margins of the circuits, because superconducting Josephson devices are very sensitive to magnetic field. In this paper, we evaluate current distribution in a superconducting ground plane by means of both experiments and numerical calculation. We also verify two methods for suppressing the ground current. One is a slot structure in the ground plane, and the other is alignment of the current-extraction point. Suppression of the ground current is quantitatively evaluated.

This paper presents the design of a driver amplifier (DA) for a cordless mouse application, operating at the 2.4 GHz ISM unlicensed band. The DA is a single-ended topology, and is composed of two stages: the first stage is a cascode amplifier to provide high gain and good input-output isolation, while the output stage is a simple common source amplifier that adopts a novel current reuse scheme to reduce the DC bias current by half. The DA implemented in a 0.18 µm CMOS process has a 16 dB gain at 2.4 GHz, and it can drive a 3 dBm to the antenna with an output stage drain efficiency of 31% and a power-added efficiency (PAE) of 20% while drawing 4.5 mA from a 1.8 V supply.

Two-dimensional (2D) communication is a novel physical communication form that utilizes the surface as a communication medium to provide both data and power transmission service to the sensor devices placed on the surface's top. In previous works, we developed 2D communication systems that utilize separated channels for data and power transmission. Though this assignment of different channels can achieve strong network performance, the sensor devices must be equipped with two or more interfaces to simultaneously receive the power and data signals, which significantly complicates and enlarges those devices. Moreover, when a channel is used for the power supply, it not only continually monopolizes the wireless frequency resource, it is also likely to cause interference with the other signal source in the case of the input power continually being sent out above a certain level. In this paper, we develop a novel 2D communication sensor system by using a single-carrier frequency for both power and data transmission, equipped with the wireless module for the two together in a compact body. To enable a sensor node that concurrently receives energy and data communication, we propose an enhancement scheme based on the IEEE802.15.4 MAC protocol standard. Through both computer simulation and actual measurement of the output power, we evaluate the performance of power supply and data transmission over the developed 2D communication sensor system.

The structure of the nanograting channel MOSFET was optimized by simply rounding the corners of the nanogratings. The current drivabilities of the optimized nanograting channel MOSFETs were enhanced by about 20% and 50% for both n-channel and p-channel MOSFETs, respectively. The mobility changes were analyzed on the basis of channel stress as well as theoretical change of mobilities by various surface orientations. The internal compressive stress of 0.23% was measured in the channel. By suppressing the electric field increase at the corner edge of the nanograting channel to less than 10%, the fabricated rounded nanograting MOSFETs achieved lifetimes of NBTI and TDDB as long as those of conventional planar devices.

This letter considers power-controlled transmission from directional antennas in mmWave wireless personal area network (WPAN) systems. The attributes of these systems are studied; these include the number of concurrent transmissions and the power consumption with different system parameters, such as the antenna's beamwidth and radiating efficiency. Numerical results are presented to show that the power controlled transmission enables more concurrent transmissions than the non-power controlled transmission. The results also show that the number of concurrent transmissions increases as the beamwidth and the path loss component become smaller and the antenna's radiating efficiency increases. In addition, the power controlled system generally uses less power than the non-power controlled transmission set up; the overall analysis is verified by simulation.

In this letter a new active element the Current Follower Transconductance Amplifier (CFTA) for the realization of the current-mode analog blocks is presented. The element is a combination of the Current Follower (CF) and the Balanced Output Transconductance Amplifier (BOTA). Possible internal structure of the CFTA is presented. The usage of the new active element is shown on the design of the Kerwin-Huelsman-Newcomb (KHN) structure working in the current mode. The frequency filter using the CFTA elements has been designed using the signal-flow graphs. The circuit structure employs three CFTA elements and two grounded passive elements. The filter enables realizing not only the basic functions as the low- (LP), band- (BP) and high-pass (HP) but also the notch and all-pass (AP) filter. The advantage of the structure presented is that the outputs of the filter are at high impedance and hence it is not necessary to use other auxiliary active elements. The properties of the filter proposed were verified by sensitivity and AC analyses in the PSPICE program.

Ba0.5Sr0.5Ta2O6 (BSTA) thin film was successfully fabricated on a Pt/SiO2/TiO2/Si substrate using the Sol-Gel method. Fundamental electrical properties of the BSTA thin film were investigated using metal-insulator-metal (MIM) structure. No diffusion of ions, from the thin film or the substrate, is observed because of the using of MIM structure. The Root Mean Square roughness of 1.04 nm shows that thin film grew well on the substrate. The BSTA thin film shows a much higher dielectric constant of about 130 than conventional gate insulators and high-k materials that are currently used in Thin Film Transistors. Low leakage current density of about 10-8 A/cm2 was obtained at an applied electric field of 500 kV/cm. Schottky emission is the dominant conduction mechanism at applied electric fields lower than 500 kV/cm and Fowler-Nordheim tunneling is the dominant conduction mechanism at higher applied electric fields. The Schottky barrier height between the Pt electrode and the Ba0.5Sr0.5Ta2O6 thin film was estimated to be 0.75 eV.

The paper presents the state of knowledge about thermal-erosion processes in contacts of low-voltage switching devices for power engineering on switching currents under short-circuit conditions. The graphical models of the short arc and the distribution of arc power introduced into contacts are shown. The method for measurements of a contact temperature during an electric discharge has been elaborated. The obtained test results are presented, i.e. changes of a contact temperature as a function of arc parameters such as current, energy, and integral ∫idt. The tests have shown that a "break point" exists on the curve expressing the relationship between a temperature rise and arc parameters in the range of high currents. The location of this point is dependent on a diameter of contacts and a value of current, and is associated with thermal energy delivered to electrodes. It has been observed that for each diameter of contacts there exists such value of an energetic quantity of arc (current, ∫idt, energy), at which diameters of arc roots are the same as a contact diameter. Above this value, the shape of a curve is changed. The obtained results explain and confirm the discontinuity of a curve expressing a contact arc erosion as a function of current, which was observed earlier by the other research workers.

The dynamic characteristics are the key issues in the optimum design of a permanent magnetic actuator (PMA). A new approach to forecast the dynamic characteristics of the multilink PMA is proposed. By carrying out further developments of ADAMS and ANSOFT, a mathematic calculation model describing the coupling of mechanical movement, electric circuit and magnetic field considering eddy current effect, is constructed. With this model, the dynamic characteristics of the multilink PMA are calculated and compared with the experimental results. Factors that affect the opening time of the multilink PMA are analyzed with the model as well. The method is capable of providing a reference for the design of the PMA.