We propose that the current distribution along a dipole can be divided into a component proportional to the port current, a component proportional to the port voltage, and an antisymmetrical component. In this paper, we perform numerical computations to verify that the component proportional to the port voltage always lags the port voltage by 90°, and the ratio of its amplitude to that of the port voltage is not significantly affected by the arrangement of other dipoles located nearby or by circuits connected to the ports of the dipoles if the dipoles have lengths not exceeding one wavelength.

This paper proposes low-power voltage-mode/current-mode hybrid circuits to realize an arbitrary two-variable logic function and a full-adder function. The voltage and current mode can be selected for low-power operations at low and high frequency, respectively, according to speed requirement. An nMOS pass transistor network is shared to realize voltage switching and current steering for the voltage- and current-mode operations, respectively, which leads to high utilization of the hardware resources. As a result, when the operating frequency is more than 1.15,GHz, the current mode of the hybrid logic circuit is more power-efficient than the voltage mode. Otherwise, the voltage mode is more power-efficient. The power consumption of the hybrid two-variable logic circuit is lower than that of the conventional two-input look-up table (LUT) using CMOS transmission gates, when the operating frequency is more than 800,MHz. The delay and area of the hybrid two-variable logic circuit are increased by only 7% and 13%, respectively

An energy-efficient intra-chip communication link circuit with ternary current signaling is proposed for an asynchronous Network-on-Chip. The data signal encoded by an asynchronous three-state protocol is represented by a small-voltage-swing three-level intermediate signal, which results in the reduction of transition delay and achieving energy-efficient data transfer. The three-level voltage is generated by using a combination of dynamically controlled current sources with feedback loop mechanism. Moreover, the proposed circuit contains a power-saving scheme where the dynamically controlled transistors also are utilized. By cutting off the current paths when the data transfer on the communication link is inactive, the power dissipation can be greatly reduced. It is demonstrated that the average data-transfer speed is about 1.5 times faster than that of a binary CMOS implementation using a 130nm CMOS technology at the supply voltage of 1.2V.

We propose a novel IDDQ outlier screening flow through a two-phase approach: a clustering-based filtering and an estimation-based current-threshold determination. In the proposed flow, a clustering technique first filters out chips that have high IDDQ current. Then, in the current-threshold determination phase, device-parameters of the unfiltered chips are estimated based on measured IDDQ currents through Bayesian inference. The estimated device-parameters will further be used to determine a statistical leakage current distribution for each test pattern and to calculate a and suitable current-threshold. Numerical experiments using a virtual wafer show that our proposed technique is 14 times more accurate than the neighbor nearest residual (NNR) method and can achieve 80% of the test escape in the case of small leakage faults whose ratios of leakage fault sizes to the nominal IDDQ current are above 40%.

General purpose computing on GPU (GPGPU) has become a popular computing model for high-performance, data-intensive applications. Accordingly, there is a strong need to develop highly efficient data structures to ease the development of GPGPU applications. In this work, we proposed an efficient concurrent queue data structure for GPU computing. The GPU based provably correct, lock-free FIFO queue allows a massive number of concurrent producers and consumers. Warp-centric en-queue and de-queue procedures are introduced to better match the underlying Single-Instruction, Multiple-Thread execution model of modern GPUs. It outperforms the best previous GPU queues by up to 40 fold. The correctness of the proposed queue operations is formally validated by linearizability criteria.

This paper proposes a generic construction of hierarchical identity-based identification (HIBI) protocols secure against impersonation under active and concurrent attacks in the standard model. The proposed construction converts a digital signature scheme existentially unforgeable against chosen message attacks, where the scheme has a protocol for showing possession of a signing key, not a signature. Our construction is based on the so-called certificate-based construction of hierarchical identity-based cryptosystems, and utilizes a variant of the well-known OR-proof technique to ensure the security against impersonation under active and concurrent attacks. We also present several concrete examples of our construction employing the Waters signature (EUROCRYPT 2005), and other signatures. As results, its concurrent security of each instantiation is proved under the computational Diffie-Hellman (CDH) assumption, the RSA assumption, or their variants in the standard model. Chin, Heng, and Goi proposed an HIBI protocol passively and concurrently secure under the CDH and one-more CDH assumption, respectively (FGIT-SecTech 2009). However, its security is proved in the random oracle model.

A low VDD current mirror with deep sub-micron vertical MOSFETs is presented. The keys are new bias circuits to reduce both the minimum VDD for the operation and the sensitivity of the output current on VDD. In the simulation, our circuits reduce the minimum VDD by about 17% and the VDD sensitivity by one order both from those of the conventional. In the simulation with 90nm φ vertical MOSFET approximate models, our circuit shows about 4MΩ output resistance at 1.2-V VDD with the small temperature dependence, which is about six times as large as that with planar MOSFETs.

We fabricated highly dense Si nano-columnar structures accompanied with Si nanocrystals on W-coated quartz and characterized their local electrical transport in the thickness direction in a non-contact mode by using a Rh-coated Si cantilever with pulse bias application, in which Vmax, Vmin, and the duty ratio were set at +3.0V, -14V, and 50%, respectively. By applying a pulse bias to the bottom W electrode with respect to a grounded top electrode made of ∼10-nm-thick Au on a sample surface, non-uniform current images in correlation with surface morphologies reflecting electron emission were obtained. The change in the surface potential of the highly dense Si nano-columnar structures accompanied with Si nanocrystals, which were measured at room temperature by using an AFM/Kelvin probe technique, indicated electron injection into and extraction from Si nanocrystals, depending on the tip bias polarity. This result is attributable to efficient electron emission under pulsed bias application due to electron charging from the top electrode to the Si nanocrystals in a positively biased duration at the bottom electrode and subsequent quasi-ballistic transport through Si nanocrystals in a negatively biased duration.

Voltage Regulator Module, called VRM is a dedicated module for supplying power to microprocessor units. Recently, significant improvement of microprocessor units arises new challenges for supplying stable power. For stable and efficient control, multiphase interleaved topology is often used in today's VRM. To achieve high performance VRM, a current sensing circuit with both high efficiency and high accuracy is demanded. To achieve high accuracy, thermal dependency is a problem to be solved. In this paper, a novel alternating voltage controlled current sensing method is proposed for suppressing thermal dependency. In the proposed method, a high frequency AC voltage is superposed on the gate-ON-voltage. Then, the AC channel current is generated, and its amplitude becomes proportional to inductor current. The AC channel current is detected through a LC filter. The proposed current sensing method is very effective for realizing a current mode control DC-DC converter. In first, we simulated the relationship between our proposed current sensing method and a electrical characteristic of a power MOSFET. We used a power MOSFET device model published by a manufacture in this simulation. From the results, we find the gate parasitic capacitance of power MOSFET effects on the sensitivity of the current sensing circuit. Besides, the power dissipation in a power MOSFET increases by the frequency of applied gate ac voltage. Moreover, the proposed current sensing circuit based on the proposed method was designed and simulated the operations by Hspice. From the results, the designed current sensing circuit based on the proposed method has enough wide sensing window from 3A to 30A for VRM applications. Moreover, comparing to the conventional current sensing circuits with the MOSFET ON-resistance, the error of the proposed current sensing circuit can be decreased over 25% near 100°C.

This paper gives a write voltage and read reference current generator considering temperature characteristics for multi-level Ge2Sb2Te5-based phase change memories. Since the optimum SET and RESET voltages linearly changes by the temperature, the voltage supply circuit must track this characteristic. In addition, the measurement results show that the read current depends on both read temperature and the write temperature and has exponential dependence on the read temperature. Thus, the binning technique is applied for each read and write temperature regions. The proposed variable TC generator can achieve below ±0.5 LSB precision from the measured differential non-linearity and integral non-linearity. As a result, the temperature characteristics of both the linear write voltage and the exponential read current can be tracked with the proposed variation tolerant linear temperature coefficient current generator.

In this work, a measurement-based procedure aimed at deriving a behavioral model of Bulk Current Injection (BCI) probes clamped onto multi-wire cable bundles is proposed. The procedure utilizes the measurement data obtained by mounting the probe onto the calibration jig for model-parameters extraction, and 2D electromagnetic simulations to adapt such parameters to the specific characteristics of the cable bundle under analysis. Outcome of the analysis is a behavioral model which can be easily implemented into the SPICE environment. Without loss of generality, the proposed model is here used to predict the radio-frequency noise stressing the terminal units of a two-wire harness. Model accuracy in predicting the common and differential mode voltages induced by BCI at the line terminals is assessed by EM modeling and simulation of the involved injection setup by the commercial software CST Microwave Studio.

Checkpoint-rollback recovery, which is a universal method for restoring distributed systems after faults, requires a sophisticated snapshot algorithm especially if the systems are large-scale, since repeatedly taking global snapshots of the whole system requires unacceptable communication cost. As a sophisticated snapshot algorithm, a partial snapshot algorithm has been introduced that takes a snapshot of a subsystem consisting only of the nodes that are communication-related to the initiator instead of a global snapshot of the whole system. In this paper, we modify the previous partial snapshot algorithm to create a new one that can take a partial snapshot more efficiently, especially when multiple nodes concurrently initiate the algorithm. Experiments show that the proposed algorithm greatly reduces the amount of communication needed for taking partial snapshots.

In this study, the influence of Gd composition on current-induced domain wall motion in a Gd-Co ferrimagnetic nanowire was theoretically investigated with taking into account of composition dependence of magnetic properties. As a result, the intrinsic critical density to move domain wall significantly reduces near the compensation composition, which is achieved to be less than 105A/cm2. Moreover, the intrinsic critical current density also significantly reduces near a certain Gd composition where the domain wall energies of Bloch and Néel walls are almost the same.

Capacitor charging modeling accelerates the time-domain simulation of power current of cryptographic VLSI circuits in a CMOS technology. The model finely represents the amount of charges consumed during the operation of Advanced Encryption Standard (AES) cores in a variety of logical implementations, reflecting their internal logical activities. This approach significantly reduces the complexity of power current simulation, and accomplishes acceleration by a factor of more than 200 over the traditional transistor-level circuit simulation. The correlated power analysis (CPA) attack against AES cores is successfully simulated with a conventional circuit simulator, with the models individually derived for 10,000 different cipher texts. The CPA is also experimentally performed against AES cores fabricated in a 65nm as well as 130nm CMOS technologies, using SASEBO measurement standards. The fast power current simulation is demonstrated to be accurate enough to evaluate the vulnerability of AES cores in various logical implementations as well as in different technologies, and exhibits general agreements with the silicon measurements.

Ocean surface current radar is a Doppler radar to observe oceanographic information using the Bragg scattering resonance mechanism. In this paper, we consider angular resolution improvement of the radar. The radar employs an antenna array with FMICW operation, then it can resolve angular distribution by Digital Beam Forming (DBF) and distance by Fourier transform of the beat signal obtained by the FMICW radar. In order to obtain sufficient angular resolution, large array length or aperture with increasing the number of elements is needed, that is often difficult to realize in the HF/VHF ocean surface current radar. In this paper we propose to apply the Khatri-Rao (KR) product array processing to the radar. To verify effectiveness of the KR product array processing in angular resolution enhancement for the ocean surface current radar, we apply the KR product array to actual experimental data set of the radar, and show that the method is available to angular resolution enhancement and Doppler spectrum improvement.

Recently, wireless power transfer has attracted much attention for power supplying on not only small electric devices but also large equipments such as electric and hybrid vehicles. Coils are important components in such power transfer systems and their AC resistance is a key factor to determine the transferring efficiency. The AC resistance of wires used in the coils is required to be as lower as possible for high efficiency systems. Copper clad aluminum (CCA) wire which has an aluminum (Al) core surrounded by a thin copper (Cu) layer has been proposed for this purpose. CCA wires are not only light-weight and easy for soldering but also show lower AC resistance than commonly used Cu wires on certain conditions. In this paper, the AC resistance caused by the skin and proximity effects of a CCA wire with circular cross-section is numerically analyzed. The condition that CCA wires are superior to Cu wires in view of AC resistance is discussed. Simulated results are compared with experiments on fabricated coils and good agreement is obtained. It is actually verified that coils wound by CCA wires have lower AC resistance than those by Cu wires under some circumstances, especially at high frequencies.

The influence of the splitter plates on the high-current arc roots formation in low voltage circuit breaker is investigated. One arc quenching chamber model is designed, where the shape of the splitter plates can be changed. The capacitor bank circuit is used to provide the test power supply, and the effective value of the prospective short circuit current is fixed to 10kA. High speed CCD camera is adopted to record the arc images during the arcing duration. Arc current and voltage are also measured to analyze the arc characteristics. In addition, a simplified 1-D thermal-electric model is developed to investigate the influence of the splitter plates on the distribution of the current density of the arc plasma with the assumption of local thermal equilibrium (LTE). It shows that the distance between the arc initial ignition location and the splitter plates is crucial to the arc root formation.

Petri nets are a kind of formal language that are widely applied in concurrent systems associated with resource allocation due to their abilities of the natural description on resource allocation and the precise characterization on deadlock. Weighted System of Simple Sequential Processes with Resources (WS3PR) is an important subclass of Petri nets that can model many resource allocation systems in which 1) multiple processes may run in parallel and 2) each execution step of each process may use multiple units from a single resource type but cannot use multiple resource types. We first prove that the liveness problem of WS3PR is co-NP-hard on the basis of the partition problem. Furthermore, we present a necessary and sufficient condition for the liveness of WS3PR based on two new concepts called Structurally Circular Wait (SCW) and Blocking Marking (BM), i.e., a WS3PR is live iff each SCW has no BM. A sufficient condition is also proposed to guarantee that an SCW has no BM. Additionally, we show some advantages of using SCW to analyze the deadlock problem compared to other siphon-based ones, and discuss the relation between SCW and siphon. These results are valuable to the further research on the deadlock prevention or avoidance for WS3PR.

This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.

With the technology scaling down, leakage power becomes an important part of total power consumption. The relatively large leakage current weakens the energy recovery capability of adiabatic circuits and reduces its superiority, compared with static CMOS circuits in the field of low-power design. In this paper, we rebuild three types of adiabatic circuits (2N2N2P, IPAL and DCPAL) based on FinFET devices to obtain a large leakage power reduction by rationally utilizing the different operating modes of FinFET devices (SG, LP, and IG). A 16-bit adiabatic adder has been investigated to demonstrate the advantages of FinFET adiabatic circuits. The Predictive Technology Model (PTM) is used for 32-nm bulk MOSFET and FinFET devices and all of the simulations are based on HSPICE. The results evince the proposed FinFET adiabatic circuits have a considerable reduction (more than 60% for SG mode FinFET and more than 80% for LP mode FinFET) of power consumption compared with the bulk MOSFET ones. Furthermore, the FinFET adiabatic circuits also have higher limiting frequency of clock source and better noise immunity.