A multiple-valued data transfer scheme using X-net is proposed to realize a compact bit-serial reconfigurable VLSI (BS-RVLSI). In the multiple-valued data transfer scheme using X-net, two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. One cell composed of a logic block and a switch block is connected to four adjacent cross points by four one-bit switches so that the complexity of the switch block is reduced to 50% in comparison with the cell of a BS-RVLSI using an eight nearest-neighbor mesh network (8-NNM). In the logic block, threshold logic circuits are used to perform threshold operations, and then their binary dual-rail voltage outputs enter a binary logic module which can be programmed to realize an arbitrary two-variable binary function or a bit-serial adder. As a result, the configuration memory count and transistor count of the proposed multiple-valued cell are reduced to 34% and 58%, respectively, in comparison with those of an equivalent CMOS cell. Moreover, its power consumption for an arbitrary 2-variable binary function becomes 67% at 800 MHz under the condition of the same delay time.

This paper presents a 20 GHz push-push VCO realized by a 10 GHz super-harmonic coupled quadrature oscillator for a quadrature 60 GHz frequency synthesizer. The output nodes are peaked by a tunable second harmonic resonator. The proposed VCO is implemented in 65 nm CMOS process. It achieves a tuning range of 3.5 GHz from 16.1 GHz to 19.6 GHz with a phase noise of -106 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 10.3 mW and an FoM of -181.3 dBc/Hz is achieved.

Circuit techniques to enhance the linearity of input-voltage-to-current (V/I) conversion and to increase the output impedance of a current source by compensating for the low intrinsic gain of a transistor were introduced to realize a high-frequency operational transconductance amplifier (OTA) for a low supply voltage using sub-100-nm CMOS processes. Applying these techniques, a MOS 7th-order Gm-C linear-phase low-pass filter (LPF) was realized using a 65 nm CMOS process. A simplified biquad LPF that can serve as a component of a 7th-order LPF was newly developed by replacing OTAs with resistors. As a result, the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion, and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, ≤ -55 dB with a 100 MHz input, and +10.3 dBm, respectively, all with a ± 0.1 Vp-p input signal at each input terminal in the pseudodifferential configuration. The LPF including an output buffer dissipated 60 mW in the case of a 1.2 V supply. Wide spurious-free dynamic range (SFDR) characteristics were confirmed up to high frequencies.

We have fabricated highly-dense Si nano-columnar structures accompanied with Si nanocrystals on W-coated quartz, and characterized their local electrical transport in the thickness direction using atomic force microscopy (AFM) with a conductive cantilever. By applying DC negative bias to the bottom W electrode with respect to a grounded top electrode made of 10-nm-thick Au on the sample surface, current images reflecting highly-localized conduction were obtained in both contact and non-contact modes. This result is attributable to electron emission due to quasi-ballistic transport through Si nanocrystals via nanocolumnar structure.

In this paper, a high performance current latch sense amplifier (CLSA) with vertical MOSFET is proposed, and its performances are investigated. The proposed CLSA with the vertical MOSFET realizes a 11% faster sensing time with about 3% smaller current consumption relative to the conventional CLSA with the planar MOSFET. Moreover, the proposed CLSA with the vertical MOSFET achieves an 1.11 dB increased voltage gain G(f) relative to the conventional CLSA with the planar MOSFET. Furthermore, the proposed CLSA realizes up to about 1.7% larger yield than the conventional CLSA, and its circuit area is 42% smaller than the conventional CLSA.

The problem of a finite monopole antenna driven by a coaxial cable is revisited. On the basis of a variable bound approach, the radiated field around a monopole antenna can be represented in terms of the discrete modal summation. This theoretical model allows us to avoid the difficulties experienced when dealing with integral equations having different wavenumber spectra and ensures a solution in a convergent series form so that it is numerically efficient. The behaviors of the input admittance and the current distribution to characterize the monopole antenna are shown for different coaxial-antenna geometries and also compared with other existing results.

This paper presents a fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator (DSM), with an analog error cancellation logic circuit, and a digital decimation filter that is fabricated using 0.18-µm CMOS technology. The 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. In the proposed differential sample-and-hold circuit, low input impedance is presented with feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror. Also, measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.200.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.

It has been reported that the temporal change of current during the deposition shows a plateau and a break, similar to those found in a photocurrent profile taken by the time-of-flight technique for the investigation of photocarrier dynamics in condensed matters, enabling the estimation of electrophoretic mobility of colloidal particles in the suspension. The estimation of the electrophoretic mobility from transient current during the deposition by the simple drift model is based on the assumption that a constant electric field is uniformly applied between the positive and negative electrodes. Therefore, it is important to check if this assumption is satisfied. It is also important to measure the temporal evolution of film thickness, because this may give information about uniformity of colloidal size in the suspension. This study addresses these topics and validity of the assumption is confirmed.

We report enhanced photocurrent properties of dye/Au-loaded titanium dioxide (TiO2) films on Au gratings. Au-loaded TiO2 nanopowders were first synthesized by a modified sol-gel method and then prepared by the impregnation method. We also fabricated dye-sensitized solar cells, which were composed of Au grating/Au-TiO2/TMPyP-SCC LbL (20 bilayers)/electrolyte/ITO substrates. Short-circuit photo-current measurements showed that Au-loaded TiO2 with grating-coupled surface plasmon excitation can enhance the short-circuit photocurrentof the fabricated cells.

With the fast development of mobile communication technologies, mobile multimedia services like mobile Video on Demand (VOD) are becoming prevalent. However, VOD streaming requires dedicated bandwidth to satisfy Quality of Service (QoS), and the limited wireless bandwidth will become insufficient to support the increasing number of mobile VOD users. In order to solve the problem, this paper proposes a Call Admission Control (CAC) approach which can accept new users even when the system bandwidth is insufficient. Our approach also guarantees continuous playback for subscribers by taking into account the service end time and the delay bound of the users. Simulation results demonstrate that the proposed scheme can increase the number of concurrent users and reduce the connection blocking probability significantly without playback interruption.

We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.

In this paper, a complete SSTA scheme is proposed to calculate the output waveform of a logic cell on any random selected point in the process variational space, or the mean value and variance of the output signal with very high accuracy and acceptable CPU cost. At first, Miller capacitances between the input nodes and internal nodes of a logic cell are introduced to construct the improved MCSM model so as to improve the modeling accuracy. Secondly, the stochastic collocation method jointed with the Modified Nested Sparse Grid technique is adopted for SSTA procedure to avoid the exponential increase of the collocation points number caused by tensor product. Thirdly, a Nominal waveform based Fast Simulation Method is developed to speedup the simulation on each collocation point. At last, Automatic Waveform Construction Technique is developed to construct the output waveform with the approximation points as little as possible to decrease the computational cost while guaranteeing high accuracy. Numerical results are also given to demonstrate the efficiency of the proposed algorithm.

This paper investigates power gating implementations that mitigate power supply noise. We focus on the body connection of power-gated circuits, and examine the amount of power supply noise induced by power-on rush current and the contribution of a power-gated circuit as a decoupling capacitance during the sleep mode. To figure out the best implementation, we designed and fabricated a test chip in 65 nm process. Experimental results with measurement and simulation reveal that the power-gated circuit with body-tied structure in triple-well is the best implementation from the following three points; power supply noise due to rush current, the contribution of decoupling capacitance during the sleep mode and the leakage reduction thanks to power gating.

A CMOS current-mode S-shape correction circuit with shape-adjustable control is proposed for suiting different LCD panel's characteristics from different manufactures. The correction shape is divided into three segments for easy curve-fitting using three lower order polynomials. Each segment could be realized by a corresponding current-mode circuit. The proposed circuit consists of several control points which are designed for tuning the correction shape. The S-shape correction circuit was fabricated using the 0.35 µm TSMC CMOS technology. The measured input dynamic range of the circuit is from 0 µA to 220 µA. The -3 dB bandwidth of the circuit is up to 262 MHz in a high input current region.

A laser irradiation experiment for photocurrent induced failure investigations was described. In order to focus a laser beam on a desired transistor, novel test circuit structures using selectively metal-covered transistors were proposed. Photocurrent induced upset failures were successfully observed in fabricated CMOS SRAM test cells. Results were discussed with SPICE simulations.

An on-chip soft-start circuit based on a switched-capacitor for DC-DC switching regulator is presented. A ramp-voltage, which is generated by a switched-capacitor, is used to make pulse width slowly increase from zero, in order to eliminate the inrush current and the overshoot voltage during start-up. The post simulation results show that the regulator soft starts well with the proposed soft-start circuit.

Reduction of the intensity noise in semiconductor lasers is an important subject for the higher performance of an application. Simultaneous usage of the superposition of high frequency current and the electric negative feedback loop was proposed to suppress the noise for the higher power operation of semiconductor lasers. Effective noise reduction of more than 25 dB with 80 mW operation was experimentally demonstrated.

Current collapse of AlGaN/GaN heterostructure field-effect transistors (HFETs) formed on qualified epitaxial layers on Si substrates was successfully suppressed using graded field-plate (FP) structures. To improve the reproducibility of the FP structure manufacturing process, a simple process for linearly graded SiO2 profile formation was developed. An HFET with a graded FP structure exhibited a significant decrease in an on-resistance increase ratio of 1.16 even after application of a drain bias of 600 V.

We propose a generic conversion from a key encapsulation mechanism (KEM) to an identification (ID) scheme. The conversion derives the security for ID schemes against concurrent man-in-the-middle (cMiM) attacks from the security for KEMs against adaptive chosen ciphertext attacks on one-wayness (one-way-CCA2). Then, regarding the derivation as a design principle of ID schemes, we develop a series of concrete one-way-CCA2 secure KEMs. We start with El Gamal KEM and prove it secure against non-adaptive chosen ciphertext attacks on one-wayness (one-way-CCA1) in the standard model. Then, we apply a tag framework with the algebraic trick of Boneh and Boyen to make it one-way-CCA2 secure based on the Gap-CDH assumption. Next, we apply the CHK transformation or a target collision resistant hash function to exit the tag framework. And finally, as it is better to rely on the CDH assumption rather than the Gap-CDH assumption, we apply the Twin DH technique of Cash, Kiltz and Shoup. The application is not “black box” and we do it by making the Twin DH technique compatible with the algebraic trick. The ID schemes obtained from our KEMs show the highest performance in both computational amount and message length compared with previously known ID schemes secure against concurrent man-in-the-middle attacks.

The authors propose a new method of controlling the isolation of an RF splitter. In the proposed method, a bias current is superimposed on an RF signal to change the permeability of the ferrite core used in the splitter's transformer. By doing this, the splitter isolation can be controlled. Experimental results have shown that superimposing a bias current of 500 mA improves device isolation by about 5 dB without affecting the loss characteristics.