In the advanced digital terrestrial/television multimedia broadcasting (DTMB-A) standard, a preamble based on distance detection (PBDD) is adopted for robust synchronization and signalling transmission. However, traditional signalling detection method will completely fail to work under severe frequency selective channels with ultra-long delay spread 0dB echoes. In this paper, a novel transmission parameter signalling detection method is proposed for the preamble in DTMB-A. Compared with the conventional signalling detection method, the proposed scheme works much better when the maximum channel delay is close to the length of the guard interval (GI). Both theoretical analyses and simulation results demonstrate that the proposed algorithm significantly improves the accuracy and robustness of detecting the transmitted signalling.

This study involves proposing a high-speed computer-generated hologram playback by using a digital micromirror device for high-definition spatiotemporal division multiplexing electroholography. Consequently, the results indicated that the study successfully reconstructed a high-definition 3-D movie of 3-D objects that was comprised of approximately 900,000 points at 60 fps when each frame was divided into twelve parts.

This paper aims to support quick and easy page access in digital documents. We tried to use a paper book as a device to navigate pages for digital documents. Our proposed system allows the users to perform the same interaction as a paper book such as inserting fingers among pages or folding an edge of the page as a dog-ear. Three experiments were conducted to confirm the effectiveness of the proposed system. As a result, we confirmed our proposed system was superior to conventional navigation methods especially in moving back and forth among pages.

This paper presents an application of low-coherence interferometry for measurement of mode field diameters (MFDs) of a few-mode fiber and shows its performance compared with another method using a mode multiplexer. We found that the presented method could measure MFDs in a few-mode fiber even without any special mode multiplexers.

Emerging digital payment services, also known as FinTech, have enabled various types of advanced payment transactions (such as Google Wallet, Apple Pay, Samsung Pay, etc.). However, offline peer-to-peer cash transactions still make up about 25.6% of the overall financial transactions in everyday life. By investigating existing online and offline payment systems, we identify three key challenges for building a digital cash transaction system with core features of the offline cash transactions: self-verifiability of digital cash; user anonymity; atomic cash transfer for double spending/depositing protection. In this paper, we propose OPERA, an offline peer-to-peer digital cash transaction system that addresses the three challenges. It newly introduces a concept of ‘one-time-readable memory(ORM)’ and ‘digital token’ which is a unit of self-verifiable digital cash. The one-time readability from ORM and three-stage token exchange protocol enable OPERA to provide uniqueness to digital cash and to allow a complete offline digital payment. OPERA devices are enhanced with TCPA technology to ensure the integrity of the physical device package. To evaluate the feasibility and resilience of the OPERA design, we built a prototype on a customized embedded board.

This paper reviews long optical reach and large capacity transmission which has become possible because of the application of wide-band and low-noise optical fiber amplifiers and digital coherent signal processing. The device structure and mechanism together with their significance are discussed.

This work develops a third-order multibit switched-current (SI) delta-sigma modulator (DSM) with a four-bit switched-capacitor (SC) flash analog-to-digital converter (ADC) and an incremental data weighted averaging circuit (IDWA), which is fabricated using 0.18µm 1P6M CMOS technology. In the proposed DSM, a 4-bit SC flash ADC is used to improve its resolution, and an IDWA is used to reduce the nonlinearity of digital-to-analog converter (DAC) by moving the quantization noise out of the signal band by first-order noise shaping. Additionally, the proposed differential sample-and-hold circuit (SH) exhibits low input impedance with feedback and width-length adjustment in the SI feedback memory cell (FMC) to increase the conversion rate. A coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate for the mirror error that is caused by the current mirror. Measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption, and chip area are 64.1 dB, 64.4 dB, 10.36 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively, with a bandwidth of 20 kHz, an oversampling ratio (OSR) of 256, a sampling frequency of 10.24 MHz, and a supply voltage of 1.8 V.

We focus on the construction of the digital signature scheme for local broadcast, which allows the devices with limited resources to securely transmit broadcast message. A multi-group authentication scheme that enables a node to authenticate its membership in multi verifiers by the sum of the secret keys has been proposed for limited resources. This paper presents a transformation which converts a multi-group authentication into a multi-group signature scheme. We show that the multi-group signature scheme converted by our transformation is existentially unforgeable against chosen message attacks (EUF-CMA secure) in the random oracle model if the multi-group authentication scheme is secure against impersonation under passive attacks (IMP-PA secure). In the multi-group signature scheme, a sender can sign a message by the secret keys which multiple certification authorities issue and the signature can validate the authenticity and integrity of the message to multiple verifiers. As a specific configuration example, we show the example in which the multi-group signature scheme by converting an error correcting code-based multi-group authentication scheme.

This paper presents FIR digital filters based on stochastic/binary hybrid computation with reduced hardware complexity and high computational accuracy. Recently, some attempts have been made to apply stochastic computation to realization of digital filters. Such realization methods lead to significant reduction of hardware complexity over the conventional filter realizations based on binary computation. However, the stochastic digital filters suffer from lower computational accuracy than the digital filters based on binary computation because of the random error fluctuations that are generated in stochastic bit streams, stochastic multipliers, and stochastic adders. This becomes a serious problem in the case of FIR filter realizations compared with the IIR counterparts because FIR filters usually require larger number of multiplications and additions than IIR filters. To improve the computational accuracy, this paper presents a stochastic/binary hybrid realization, where multipliers are realized using stochastic computation but adders are realized using binary computation. In addition, a coefficient-scaling technique is proposed to further improve the computational accuracy of stochastic FIR filters. Furthermore, the transposed structure is applied to the FIR filter realization, leading to reduction of hardware complexity. Evaluation results demonstrate that our method achieves at most 40dB improvement in minimum stopband attenuation compared with the conventional pure stochastic design.

An energy-efficient nonvolatile FPGA with assuring highly-reliable backup operation using a self-terminated power-gating scheme is proposed. Since the write current is automatically cut off just after the temporal data in the flip-flop is successfully backed up in the nonvolatile device, the amount of write energy can be minimized with no write failure. Moreover, when the backup operation in a particular cluster is completed, power supply of the cluster is immediately turned off, which minimizes standby energy due to leakage current. In fact, the total amount of energy consumption during the backup operation is reduced by 66% in comparison with that of a conventional worst-case-based approach where the long time write current pulse is used for the reliable write.

In this paper, we propose a novel method for the design of CSD (Canonic Signed Digit) coefficient FIR (Finite Impulse Response) filters based on ACO (Ant Colony Optimization). This design problem is formulated as a combinatorial optimization problem and requires high computation time to obtain the optimal solution. Therefore, we propose an ACO approach for the design of CSD coefficient FIR filters. ACO is one of the promising approaches and appropriate for solving a combinatorial optimization problem in reasonable computation time. Several design examples showed the effectiveness of our method.

A comprehensive method applying a nonlinear frequency compression (FC) as complementary to multi-band loudness compensation is proposed, which is able to improve loudness compensation and simultaneously increase high-frequency speech intelligibility for digital hearing aids. The proposed nonlinear FC (NLFC) improves the conventional methods in the aspect that the compression ratio (CR) is adjusted based on the speech intelligibility percentage in different frequency ranges. Then, an adaptive wide dynamic range compression (AWDRC) with a time-varying CR is applied to achieve adaptive loudness compensation. The experimental test results show that the mean speech identification is improved in comparison with the state-of-art methods.

Linear phase maximally flat digital differentiators (DDs) with stopbands obtained by minimizing the Lp norm are filters with important practical applications, as they can differentiate input signals without distortion. Stopbands designed by minimizing the Lp norm can be used to control the relationship between the steepness in the transition band and the ripple scale. However, linear phase DDs are unsuitable for real-time processing because each group delay is half of the filter order. In this paper, we proposed a design method for a low-delay maximally flat low-pass/band-pass FIR DDs with stopbands obtained by minimizing the Lp norm. The proposed DDs have low-delay characteristics that approximate the linear phase characteristics only in the passband. The proposed transfer function is composed of two functions, one with flat characteristics in the passband and one that ensures the transfer function has Lp approximated characteristics in the stopband. In the optimization of the latter function, Newton's method is employed.

This paper presents a high resolution mixed-domain Delta-Sigma (ΔΣ) time-to-digital converter (TDC) which utilizes a charge pump as time-to-voltage converter, a low resolution SAR ADC as quantizer, and a pair of delay-line digital-to-time converters to form a negative feedback. By never resetting the sampling capacitor of the charge-pump, an integrator is realized and first order noise shaping can be achieved. However, since the integrating capacitor is never cleared, this circuit is prone to charge-sharing issue during input sampling which can degrade TDC's performance. To deal with this issue, a compensation circuit consists of another pair of sampling capacitors and charge-pumps with doubled current is proposed. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 2.5 MHz bandwidth, simulation shows that this TDC achieves 66.4 dB SNDR and 295 fsrms integrated noise for ±1 ns input range. The proposed TDC consumes 1.78 mW power that translates to FoM of 208 fJ/conv.

The 1-bit band-pass delta-sigma modulator (BP-DSM) achieves high resolution by using the oversampling technique. This method allows direct RF signal transmission from a digitally modulated signal, using a 1-bit digital pulse train. However, it has been previously reported that the adjacent channel leakage ratio (ACLR) in a target frequency band degrades due to the pulse transition mismatch between rising and falling waveforms in the time domain. This paper clarifies that the spurious distortion in BP-DSM is caused by the asymmetricity of the waveform about the center of an eye pattern in the time axis, and proposes a 1-bit BP-DSM with the compensator consisting of a fractional delay filter and a binary data differentiator to cancel out the asymmetry in the target frequency band. This can accurately provide a wideband cancellation signal with more than 100MHz bandwidth, including the adjacent channel, within 50dB power dynamic range. Using long term evolution (LTE) signals with 5MHz bandwidth at 0.8GHz, we simulated the spurious distortion, performing various combinations of rising and falling times in the eye pattern, and the proposed 1-bit BP-DSM always achieved high ACLR, up to 60dB, in 140MHz bandwidth, under all conditions.

We evaluated a technique for protecting the copyright of digital data for 3-D printing. To embed copyright information, the inside of a 3-D printed object is constructed from fine domains that have different physical characteristics from those of the object's main body surrounding them, and to read out the embedded information, these fine domains inside the objects are detected using nondestructive inspections such as X-ray photography or thermography. In the evaluation, copyright information embedded inside the 3-D printed object was expressed using the depth of fine cavities inside the object, and X-ray photography were used for reading them out from the object. The test sample was a cuboid 46mm wide, 42mm long, and 20mm deep. The cavities were 2mm wide and 2mm long. The difference in the depths of the cavities appeared as a difference in the luminance in the X-ray photographs, and 21 levels of depth could be detected on the basis of the difference in luminance. These results indicate that under the conditions of the experiment, each cavity expressed 4 to 5bits of information with its depth. We demonstrated that the proposed technique had the possibility of embedding a sufficient volume of information for expressing copyright information by using the depths of cavities.

This paper first reviews the state-of-the-art noise reduction methods and points out their vulnerability in noise reduction performance and speech quality, especially under the low signal-noise ratios (SNR) environments. Then this paper presents an improved perceptual multiband spectral subtraction (MBSS) noise reduction algorithm (NRA) and a novel robust voice activity detection (VAD) based on the amended sub-band SNR. The proposed SNR-based VAD can considerably increase the accuracy of discrimination between noise and speech frame. The simulation results show that the proposed NRA has better segmental SNR (segSNR) and perceptual evaluation of speech quality (PESQ) performance than other noise reduction algorithms especially under low SNR environments. In addition, a fully operational digital hearing aid chip is designed and fabricated in the 0.13 µm CMOS process based on the proposed NRA. The final chip implementation shows that the whole chip dissipates 1.3 mA at the 1.2 V operation. The acoustic test result shows that the maximum output sound pressure level (OSPL) is 114.6 dB SPL, the equivalent input noise is 5.9 dB SPL, and the total harmonic distortion is 2.5%. So the proposed digital hearing aid chip is a promising candidate for high performance hearing-aid systems.

The purpose of this paper is to propose a flexible load-dependent digital soft-start control method for dc-dc converters in a 380Vdc system. The soft-start operation is needed to prevent negative effects such as large inrush current and output overshoot to a power supply in the start-up process of dc-dc converters. In the conventional soft-start operation, a dc-dc converter has a very slow start-up to deal with the light load condition. Therefore, it always takes a long time in any load condition to start up a power supply and obtain the desired output. In the proposed soft-start control method, the speed of the start-up process is flexibly controlled depending on the load condition. To obtain the optimal speed for any load condition, the speed of the soft-start is determined from a approximated function of load current, which is estimated from experiment results in advance. The proposed soft-start control method is evaluated both in simulations and experiments. From results, it is confirmed that the proposed method has superior soft-start characteristics compared to the conventional one.

We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.

An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.