A novel dynamic element matching (DEM) method, called binary-tree random DEM (BTR-DEM), is presented for a Nyquist-rate current-steering digital-to-analog converter (DAC). By increasing or decreasing the number of unit current sources randomly at the same time, the BTR-DEM encoding reduces switch transition glitches. A 5-bit current-steering DAC with the BTR-DEM technique is implemented in a 65-nm CMOS technology. The measured spurious free dynamic range (SFDR) attains 42 dB for a sample rate of 100 MHz and shows little dependence on signal frequency.

This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27×0.36mm2, is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25°C is 3µs. The average reduction energy is at least 42% from 0°C to 100°C.

A high energy-efficiency and area-reduction switching scheme for a low-power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. Based on the sequence initialization, monotonic capacitor switching procedure and multiple reference voltages, the average switching energy and total capacitance of the proposed scheme are reduced by 99.4% and 87.5% respectively, compared to the conventional architecture.

Neural networks are widely used in various fields due to their superior learning abilities. This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL), and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a global winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the WTA in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning.

This paper proposes a voice activity detection (VAD) algorithm based on an energy related feature of the frequency modulation of harmonics. A multi-resolution spectro-temporal analysis framework, which was developed to extract texture features of the audio signal from its Fourier spectrogram, is used to extract frequency modulation features of the speech signal. The proposed algorithm labels the voice active segments of the speech signal by comparing the energy related feature of the frequency modulation of harmonics with a threshold. Then, the proposed VAD is implemented on one of Texas Instruments (TI) digital signal processor (DSP) platforms for real-time operation. Simulations conducted on the DSP platform demonstrate the proposed VAD performs significantly better than three standard VADs, ITU-T G.729B, ETSI AMR1 and AMR2, in non-stationary noise in terms of the receiver operating characteristic (ROC) curves and the recognition rates from a practical distributed speech recognition (DSR) system.

In this letter we present an imperceptible and robust watermarking algorithm that uses a cryptographic hash function in the authentication application of digital medical imaging. In the proposed scheme we combine discrete Fourier transform (DFT) and local image masking to detect the watermark after a geometrical distortion and improve its imperceptibility. The image quality is measured by metrics currently used in digital image processing, such as VSNR, SSIM and PSNR.

This paper presents a cell-based all-digital phase-locked loop (ADPLL) with hierarchical gated digitally controlled oscillator (G-DCO) for low voltage operation, wide frequency range as well as low-power consumption. In addition, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed to estimate the output frequency in 1.5MF (MF = 3 in this paper) cycles and this fast lock-in time is suitable to the dynamic voltage frequency scaling (DVFS) systems. A hierarchical G-DCO is proposed to work at low supply voltage to reduce the power consumption and at the same time to achieve wide frequency range and precise frequency resolution. The core area of the proposed ADPLL is 0.02635 mm2. In near-threshold region (VDD = 0.36 V), the proposed ADPLL only dissipates 68.2 µW and has a rms period jitter of 1.25% UI at 60 MHz output clock frequency. Under 0.5 V VDD operation, the proposed ADPLL dissipates 404.2 µW at 400 MHz. The fast lock-in time of 4.489 µs and the low jitter performance below 0.5% UI at 400 MHz output clock frequency in the proposed ADPLL are suitable in event-driven or DVFS applications.

We investigate a quantization error improvement technique using a dual rail configuration for optical quantization. Our proposed optical quantization uses intensity-to-wavelength conversion based on soliton self-frequency shift and spectral compression based on self-phase modulation. However, some unfavorable input peak power regions exist due to stagnations of wavelength shift or distortions of spectral compression. These phenomena could induce a serious quantization error and degrade the effective number of bit (ENOB). In this work, we propose a quantization error improvement technique which can make up for the unfavorable input peak power regions. We experimentally verify the quantization error improvement effect by the proposed technique in 6 bit optical quantization. The estimated ENOB is improved from 5.35 bit to 5.66 bit. In addition, we examine the XPM influence between counter-propagating pulses at high sampling rate. Experimental results and numerical simulation show that the XPM influence is negligible under ∼40 GS/s conditions.

We propose a method of spread spectrum digital watermarking with quantization index modulation (QIM) and evaluate the method on the basis of IHC evaluation criteria. The spread spectrum technique can make watermarks robust by using spread codes. Since watermarks can have redundancy, messages can be decoded from a degraded stego-image. Under IHC evaluation criteria, it is necessary to decode the messages without the original image. To do so, we propose a method in which watermarks are generated by using the spread spectrum technique and are embedded by QIM. QIM is an embedding method that can decode without an original image. The IHC evaluation criteria include JPEG compression and cropping as attacks. JPEG compression is lossy compression. Therefore, errors occur in watermarks. Since watermarks in stego-images are out of synchronization due to cropping, the position of embedded watermarks may be unclear. Detecting this position is needed while decoding. Therefore, both error correction and synchronization are required for digital watermarking methods. As countermeasures against cropping, the original image is divided into segments to embed watermarks. Moreover, each segment is divided into 8×8 pixel blocks. A watermark is embedded into a DCT coefficient in a block by QIM. To synchronize in decoding, the proposed method uses the correlation between watermarks and spread codes. After synchronization, watermarks are extracted by QIM, and then, messages are estimated from the watermarks. The proposed method was evaluated on the basis of the IHC evaluation criteria. The PSNR had to be higher than 30 dB. Ten 1920×1080 rectangular regions were cropped from each stego-image, and 200-bit messages were decoded from these regions. Their BERs were calculated to assess the tolerance. As a result, the BERs were less than 1.0%, and the average PSNR was 46.70 dB. Therefore, our method achieved a high image quality when using the IHC evaluation criteria. In addition, the proposed method was also evaluated by using StirMark 4.0. As a result, we found that our method has robustness for not only JPEG compression and cropping but also additional noise and Gaussian filtering. Moreover, the method has an advantage in that detection time is small since the synchronization is processed in 8×8 pixel blocks.

A forward/reverse body bias generator (BBG) which operates under wide supply-range is proposed. Fine-grained body biasing (FGBB) is effective to reduce variability and increase energy efficiency on digital LSIs. Since FGBB requires a number of BBGs to be implemented, simple design is preferred. We propose a BBG with charge pumps for reverse body bias and the BBG operates under wide supply-range from 0.5,V to 1.2,V. Layout of the BBG was designed in a cell-based flow with an AES core and fabricated in a 65~nm CMOS process. Area of the AES core is 0.22 mm$^2$ and area overhead of the BBG is 2.3%. Demonstration of the AES core shows a successful operation with the supply voltage from 0.5,V to 1.2,V which enables the reduction of power dissipation, for example, of 17% at 400,MHz operation.

In this paper, the importance and perspective for the digitally-assisted analog and RF circuits are discussed, especially related to wireless transceivers. Digital calibration techniques for compensating I/Q mismatch, IM2, and LO impairments in cellular, 2.4,GHz WiFi, and 60,GHz WiGig transceivers are introduced with detailed analysis and circuit implementations. Future technology directions such as the shift from digitally-assisted analog circuit to digitally-designed analog circuit will also be discussed.

This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18,$mu $m 1P6M CMOS process, with the core area of 0.093,mm$^{mathrm{2}}$. The output frequency had a range of 43.4,MHz, extasciitilde 225.8,MHz at 1.8,V with peak-to-peak jitter (Pk-Pk) jitter 139.2,ps at 225.8,MHz. Power consumption is 2.8,mW @ 225.8,MHz with 1.8 supply voltage.

In this letter, we present an authentication and recovery scheme to protect images. The image blocks are DCT transformed and then encoded with different patterns. An optimal selection is adopted to find the best pattern for each block which results in better image quality. Both the recovery and check data are embedded for data protection. The experimental results demonstrate that our method is able to identify and localize regions having been tampered with. Furthermore, good image quality for both watermarked and recovered images are effectively preserved.

In this paper we describe and experimentally validate a dual-band digital predistortion (DPD) model we propose that takes account of the intermodulation and harmonic distortion produced when the center frequencies of input bands have a harmonic relationship. We also describe and experimentally validate our proposed novel dual-band power amplifier (PA) linearization architecture consisting of a single feedback loop employing a dual-band mixer. Experiment results show that the DPD linearization the proposed model provides can compensate for intermodulation and harmonic distortion in a way that the conventional two-dimensional (2-D) DPD approach cannot. The proposed feedback architecture should make it possible to simplify analog-to-digital converter (ADC) design and eliminate the time lag between different feedback paths.

An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely “4-Clock-Edge-Shift Construction” (4CKES). TAD features superior voltage sensitivity and 1st-order noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65nm CMOS, and consumes a small area of 0.016mm2. It achieves a voltage resolution of 82.7µV/LSB at 10MS/s and 1.96µV/LSB at 200kS/s in a narrow input range of 0.1Vpp, merely under 0.6V supply. The highest SNR of TAD prototype is 61.36dB in 20kHz bandwidth at 10MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.

For digital forensic investigations, the proposed scheme verifies the integrity of video contents in legacy surveillance camera systems with no built-in integrity protection. The scheme exploits video frames remaining in slack space of storage media, instead of timestamp information vulnerable to tampering. The scheme is applied to integrity verification of video contents formatted with AVI or MP4 files in automobile blackboxes.

A 10-gigabit Ethernet passive optical network (10G-EPON) is promising for the next generation of access networks. A protocol processor for 10G-EPON needs to not only achieve 10-Gbps throughput but also to have protocol extendibility for various potential services. However, the conventional protocol processor does not have the ability to install additional protocols after chip fabrication, due to its hardware-based architecture. This paper presents a software-hardware cooperative protocol processor for 10G-EPON that provides the protocol extendibility. To achieve the software-hardware cooperation, the protocol processor newly employs a software-hardware partitioning technique driven by the timing requirements of 10G-EPON and a software-hardware interface circuit with event FIFO to absorb performance difference between software and hardware. The fabricated chip with this protocol processor properly works cooperatively and is able to accept newly standardized protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services.

In digital cinema, an image goes through many types of processes like scanning, mastering, and digital intermediate. Among them, the digital intermediate process plays a central role because it determines the final color of an image. It edits and changes the colors of the images. However, some color distortions such as color bleeding are generated when editing and changing local colors in an image. In this paper, local color improvement for digital intermediate is proposed based on color transfer. Our method is simple and efficient color improvement that does not requires neither precise image segmentation nor feature matching. To prevent color distortions, a modified color influence map is proposed with color categories. First, the source image is roughly segmented using a color category map, which groups similar colors in color space. Second, the color influence map is modified by assigning different weights to the lightness and chroma components. Lastly, the modified color influence map and color category map filtered with anisotropic diffusion are combined. Experimental results show that the proposed method produces less color distortion in the resulting image.

For a large-sized touch screen, we designed and evaluated a real-time touch microarchitecture using a field-programmable gate array (FPGA). A high-speed hardware accelerator based on a parallel touch algorithm is suggested and implemented in this letter. The touch controller also has a timing control unit and an analog digital convert (ADC) control unit for analog touch sensing circuits. Measurement results of processing time showed that the touch controller with its proposed microarchitecture is five times faster than the 32-bit reduced instruction set computer (RISC) processor without the touch accelerator.

Multimedia contents can be enriched by introducing navigation with image codes readable by camera-mounted mobile devices such as smartphones. Data hiding technologies were utilized for embedding such codes to make their appearances inconspicuous, which can reduce esthetic damage on visual media. This article proposes a method of embedding two-dimensional codes into images based on successive color mixture for a blue-color channel. This technology can make the color of codes mimic those used on a cover image, while preserving their readability for current general purpose image sensors.