A digital background calibration technique using signal-dependent dithering is proposed, to correct the nonlinear errors which results from capacitor mismatches and finite opamp gain in pipelined analog-to-digital converter (ADC). Large magnitude dithers are used to measure and correct both errors simultaneously in background. In the proposed calibration system, the 2.5-bit capacitor-flip-over multiplying digital-to-analog converter (MDAC) stage is modified for the injection of large magnitude dithering by adding six additional comparators, and thus only three correction parameters in every stage subjected to correction were measured and extracted by a simple calibration algorithm with multibit first stage. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio improves from 63.3 to 79.3dB and the spurious-free dynamic range is increased from 63.9 to 96.4dB after calibrating the first two stages, in a 14-bit 100-MS/s pipelined ADC with σ=0.2% capacitor mismatches and 60dB nonideal opamp gain. The time of calibrating the first two stages is around 1.34 seconds for the modeled ADC.

We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.

This paper presents an implementation of a digital chaotic signal generator based on compound one-dimensional sinusoidal maps. The proposed chaotic map not only offers high chaoticity measured from a positive lyapunov exponent but also provides diverse bifurcation structures with robust chaos over most regions of parameter spaces. Implementation on FPGA realizes small number of components and offers a highly random chaotic sequence with no autocorrelation. The proposed chaotic signal generator offers a potential alternative in random test pattern generation or in secured data communication applications.

A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0.6V to 1.2V. We fabricated the BBG in a 65nm CMOS process to control 0.1mm2 of core circuit with the area overhead of 1.4% for the BBG.

This letter proposes an efficient compression scheme for the copyright- and privacy-protected image trading system. The proposed scheme multiplies pseudo random signs to amplitude components of discrete cosine transformed coefficients before the inverse transformation is applied. The proposed scheme efficiently compresses amplitude-only image which is the inversely transformed amplitude components, and the scheme simultaneously improves the compression efficiency of phase-only image which is the inversely transformed phase components, in comparison with the conventional systems.

Combining the strong anti-interference advantages of OFDM technology and the time-frequency analysis features of fractional Fourier transform (FFT), we apply OFDM as the coding modulation technology for digital watermarking. Based on the Arnold scrambling and OFDM coding, an innovative DFRFT digital watermarking algorithm is proposed. First, the watermark information is subjected to the Arnold scrambling encryption and OFDM coding transform. Then it is embedded into the FFT domain amplitude. The three parameters of scrambling iterations number, t, FFT order, p, and the watermark information embedded position, L, are used as keys, so that the algorithm has high safety. A simulation shows that the algorithm is highly robust against noise, filtering, compression, and other general attacks. The algorithm not only has strong security, but also makes a good balance between invisibility and robustness. But the possibility of using OFDM technique in robust image watermarking has drawn a very little attention.

With the increasing demand for geographic information and position information, the geographic information system (GIS) has come to be widely used in city planning, utilities management, natural resource environments, land surveying, etc. While most GIS maps use vector data to represent geographic information more easily and in greater detail, a GIS vector map can be easily copied, edited, and illegally distributed, like most digital data. This paper presents an invisible, blind, secure, and robust watermarking method that provides copyright protection of GIS vector digital maps by means of arc length distribution. In our method, we calculate the arc lengths of all the polylines/polygons in a map and cluster these arc lengths into a number of groups. We then embed a watermark bit by changing the arc length distribution of a suitable group. For greater security and robustness, we use a pseudo-random number sequence for processing the watermark and embed the watermark multiple times in all maps. Experimental results verify that our method has good invisibility, security, and robustness against various geometric attacks and that the original map is not needed in the watermark extraction process.

Multivariate Public Key Cryptosystems (MPKC) are candidates for post-quantum cryptography. Rainbow is a digital signature scheme in MPKC, whose signature generation and verification are relatively efficient. However, the security of MPKC depends on the difficulty in solving a system of multivariate polynomials, and the key length of MPKC becomes substantially large compared with that of RSA cryptosystems for the same level of security. The size of the secret and public keys in MPKC has been reduced in previous research. The NC-Rainbow is a signature scheme in MPKC, which was proposed in order to reduce the size of secret key of Rainbow. So far, several attacks against NC-Rainbow have been proposed. In this paper, we summarize attacks against NC-Rainbow, containing attacks against the original Rainbow, and analyze the total security of NC-Rainbow. Based on the cryptanalysis, we estimate the security parameter of NC-Rainbow at the several security level.

In this paper, a new digital true random number generator based on Cross Feedback Ring Oscillators (CFRO) is proposed. The random sources of CFRO lie in delay variations (jitter), unpredictable transition behaviors as well as metastability. The CFRO is proved to be truly random by restarting from the same initial states. Compared with the so-called Fibonacci Ring Oscillator (FIRO) and Galois Ring Oscillator (GARO), the CFRO needs less than half of their time to accumulate relatively high entropy and enable extraction of one random bit. Only a simple XOR corrector is used to reduce the bias of output sequences. TRNG based on CFRO can be run continuously at a constant high speed of 150Mbps. For higher security, the TRNG can be set in stateless mode at a cost of slower speed of 10Mbps. The total logical resources used are relatively small and no special placement and routing is needed. The TRNG both in continuous mode and in stateless mode can pass the NIST tests and the DIEHARD tests.

This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6mW, almost half of the folded cascode amplifier satisfying 12-bit, 400MS/s ADC operation. Moreover, the proposed amplifier secures 600mV output swing, which is one drain source voltage (VDS) wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using the proposed amplifier is fabricated in a 1P9M 90nm CMOS technology with a 1.2V supply voltage. The ADC achieves an effective number of bit (ENOB) of about 10-bit at 300MS/s and an figure of merit (FoM) of 0.2pJ/conv. when the frequency of the input signal is sufficiently low.

LT codes are the first practical rateless codes whose reception overhead totally depends on the degree distribution adopted. The capability of LT codes with a particular degree distribution named robust soliton has been theoretically analyzed; it asymptotically approaches the optimum when the message length approaches infinity. However, real applications making use of LT codes have finite number of input symbols. It is quite important to refine degree distributions because there are distributions whose performance can exceed that of the robust soliton distribution for short message length. In this work, a practical framework that employs evolutionary algorithms is proposed to search for better degree distributions. Our experiments empirically prove that the proposed framework is robust and can customize degree distributions for LT codes with different message length. The decoding error probabilities of the distributions found in the experiments compare well with those of robust soliton distributions. The significant improvement of LT codes with the optimized degree distributions is demonstrated in the paper.

Digital watermarking techniques have been used to assert the ownerships of digital images. The ownership information is embedded in an image as a watermark so that the owner of the image can be identified. However, many types of attacks have been used in attempts to break or remove embedded watermarks. Therefore, the watermark should be very robust against various kinds of attacks. Among them, the print-and-scan (PS) attack is very challenging because it not only alters the pixel values but also changes the positions of the original pixels. In this paper, we propose a watermarking system operating in the discrete cosine transform (DCT) domain. The polarities of the DCT coefficients are modified for watermark embedding. This is done by considering the properties of DCT coefficients under the PS attack. The proposed system is able to maintain the image quality after watermarking and the embedded watermark is very robust against the PS attack as well.

This paper presents an automatic gain control (AGC) system suitable for 60GHz direct conversion receivers. By using a two step gain control algorithm with high-pass filter cutoff frequency switching, the proposed AGC system realizes fast settling time and wide dynamic range simultaneously. The paper also discusses wide-bandwidth variable gain amplifier (VGA) design. By introducing digitally-controlled resistors and gain flattening capacitors, the proposed VGA realizes wide gain range while compensating gain variations due to parasitic capacitance of MOS switches. The AGC system is implemented in a transceiver chipset where RFIC and BBIC are fabricated in 90nm CMOS and 40nm CMOS respectively. The measurement shows excellent dynamic range of 47dB with +/-1dB gain accuracy within 1µs settling time, which satisfies the stringent requirements of the IEEE802.11ad standard.

This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.

This paper proposes a coarse-fine Time-to-Digital Converter (TDC), based on a Ring-Tapped Delay Line (RTDL). The TDC achieves the picosecond's level timing resolution and microsecond's level dynamic range at low cost. The TDC is composed of two coarse time measurement blocks, a time residue generator, and a fine time measurement block. In the coarse blocks, RTDL is constructed by redesigning the conventional Tapped Delay Line (TDL) in a ring structure. A 12-bit counter is employed in one of the two coarse blocks to count the cycle times of the signal traveling in the RTDL. In this way, the input range is increased up to 20.3µs without use of an external reference clock. Besides, the setup time of soft-edged D-flip-flops (SDFFs) adopted in RTDL is set to zero. The adjustable time residue generator picks up the time residue of the coarse block and propagates the residue to the fine block. In the fine block, we use a Vernier Ring Oscillator (VRO) with MOS capacitors to achieve a scalable timing resolution of 11.8ps (1 LSB). Experimental results show that the measured characteristic curve has high-level linearity; the measured DNL and INL are within ± 0.6 LSB and ± 1.5 LSB, respectively. When stimulated by constant interval input, the standard deviation of the system is below 0.35 LSB. The dead time of the proposed TDC is less than 650ps. When operating at 5 MSPS at 3.3V power supply, the power consumption of the chip is 21.5mW. Owing to the use of RTDL and VRO structures, the chip core area is only 0.35mm × 0.28mm in a 0.35µm CMOS process.

A specification for digital cinema systems which deal with movies digitally from production to delivery as well as projection on the screens is recommended by DCI (Digital Cinema Initiative), and the systems based on this specification have already been developed and installed in theaters. The parameters of the systems that play an important role in determining image quality include image resolution, quantization bit depth, color space, gamma characteristics, and data compression methods. This paper comparatively discusses a relation between required bit depth and gamma quantization using both of a human visual system for grayscale images and two color difference models for color images. The required bit depth obtained from a contrast sensitivity function against grayscale images monotonically decreases as the gamma value increases, while it has a minimum value when the gamma is 2.9 to 3.0 from both of the CIE 1976 L* a* b* and CIEDE2000 color difference models. It is also shown that the bit depth derived from the contrast sensitivity function is one bit greater than that derived from the color difference models at the gamma value of 2.6. Moreover, a comparison between the color differences computed with the CIE 1976 L* a* b* and CIEDE2000 leads to a same result from the view point of the required bit depth for digital cinema systems.

For source camera identification, we propose a method to reconstruct the sensor pattern noise map from a size-reduced query image by minimizing an objective function derived from the observation model. Our method can be applied to multiple queries, and can thus be further improved. Experiments demonstrate the superiority of the proposed method over conventional interpolation-based magnification algorithms.

This letter studies a digital return map that is a mapping from a set of lattice points to itself. The digital map can exhibit various periodic orbits. As a typical example, we present the digital logistic map based on the logistic map. Two fundamental results are shown. When the logistic map has a unique periodic orbit, the digital map can have plural periodic orbits. When the logistic map has an unstable period-3 orbit that causes chaos, the digital map can have a stable period-3 orbit with various domain of attractions.

We propose a composite DCT basis line test signal to evaluate the video quality of a DTV encoder. The proposed composite test signal contains a frame index, a calibration square wave, and 7-field basis signals. The results show that the proposed method may be useful for an in-service video quality verifier, using an ordinary oscilloscope instead of special equipment.

This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.