Maximally flat digital differentiators (MFDDs) are widely used in many applications. By using MFDDs, we obtain the derivative of an input signal with high accuracy around their center frequency of flat property. Moreover, to avoid the influence of noise, it is desirable to attenuate the magnitude property of MFDDs expect for the vicinity of the center frequency. In this paper, we introduce a design method of linear phase FIR band-pass MFDDs with an arbitrary center frequency. The proposed transfer function for both of TYPE III and TYPE IV can be achieved as a closed form function using Jacobi polynomial. Furthermore, we can easily derive the weighting coefficients of the proposed MFDDs using recursive formula. Through some design examples, we confirm that the proposed method can adjust the center frequency arbitrarily and the band width having flat property.

This paper presents an adaptive feedback canceller (AFC) based on a pseudo affine projection (PAP) algorithm that can provide fast and stable adaptation to the time-varying environment. The proposed algorithm utilizes the adaptive linear prediction (LP) to obtain the LP coefficients of input signal model and the inverse gain filter (IGF) to alleviate the effect of compensation gain. As a result, when the input is model as an AR signal, the proposed algorithm satisfies the condition for having an almost unbiased estimatie of the feedback path and then its performance is relatively independent of the gain setting of hearing aids. Simulation results showed that the proposed algorithm is capable of obtaining unbaised feedback path estimates and high speech quality.

In the digital terrestrial TV broadcasting system, it is important to evaluate both quantitative levels and sources of overreach interference, because it can degrade the TV service quality. This paper newly proposes an overreach measurement method that simultaneously monitors RSSI (Received Signal Strength Indicator) and CNR (Carrier to Noise power Ratio) of the TV waves and RSSI of FM waves. The results of measurements conducted in Hiroshima prefecture show that our proposed method can evaluate the level of overreach interference in the TV waves and also identify the source of the interference. Total 43 overreach interference events were found in the proposed method from one-year measurement in 2012. Based on M profile data, this paper also shows that the main factor of the overreach interference in this measurement is duct propagation due to meteorological condition.

In the traditional microphone array signal processing, the performance degrades rapidly when the array aperture decreases, which has been a barrier restricting its implementation in the small-scale acoustic system such as digital hearing aids. In this work a new compressed sampling method of miniature microphone array is proposed, which compresses information in the internal of ADC by means of mixture system of hardware circuit and software program in order to remove the redundancy of the different array element signals. The architecture of the method is developed using the Verilog language and has already been tested in the FPGA chip. Experiments of compressed sampling and reconstruction show the successful sparseness and reconstruction for speech sources. Owing to having avoided singularity problem of the correlation matrix of the miniature microphone array, when used in the direction of arrival (DOA) estimation in digital hearing aids, the proposed method has the advantage of higher resolution compared with the traditional GCC and MUSIC algorithms.

Digital coherent receivers have gained significant attention in the last decade. The reason for this is that coherent detection, along with digital signal processing (DSP) allows for substantial increase of the channel capacity by employing advanced detection techniques. In this paper, we first review coherent detection technique employed in the receiver as well as the required receiver structure. Subsequently, we describe the core part of the receiver — DSP algorithms — that are used for data processing. We cover all basic elements of a conventional coherent receiver DSP chain: deskew, orthonormaliation, chromatic dispersion compensation/nonlinear compensation, resampling and timing recovery, polarization demultiplexing and equalization, frequency and phase recovery, digital demodulation. We also describe novel subsystems of a digital coherent receiver: modulation format recognition and impairment mitigation via expectation maximization, which may gain popularity with increasing importance of autonomous networks.

In this paper, a 1.8-V 10-bit 100,MS/s successive approximation register (SAR) analog-to-digital converter (ADC) simulated in a TSMC 0.18-$mu$m CMOS process is presented. By applying ten comparators followed by an asynchronous trigger logic, the proposed SAR ADC achieves high speed operation. Compared to the conventional SAR ADC, there is no significant delay in the digital feedback logic in this design. With the sampling rate limited only by the ten delays of the capacitor DAC settling and comparators quantization, the proposed SAR ADC achieves a peak SNDR of 61.2,dB at 100,MS/s and 80,MS/s, consuming 3.2,mW and 3.1,mW respectively.

A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced~(HCI) degradation is presented. The supply voltage of the last stage of the PA ($V_{{ m PA}}$) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21,mm$^{2}$, which provides a saturation power of 10.1,dBm to 13.2,dBm with a peak power-added efficiency~(PAE) of 8.1% to 15.0% for the supply voltage $V_{{ m PA}}$ which varies from 0.7,V to 1.0,V at 60,GHz, respectively.

A novel auto-tuning digital DC--DC converter is presented. In order to reduce the recovery time and undershoot, the auto-tuning control combines LnL, conventional PID and a predictive PID with a configurable predictive coefficient. A switch module is used to select an algorithm from the three control algorithms, according to the difference between the error signal and the two initially predefined thresholds. The detection and control logic is designed for both window delay line ADC and $Sigma Delta$ DPWM to correct the delay deviation. When the output of the converter exceeds the quantization range, the digital output of ADC is set at 0 or 1, and the delay line stops working to reduce power consumption. Theoretical analysis and simulations in the CSMC CMOS 0.5,$mu$m process are carried out to verify the proposed DC--DC converter. It is found that the converter achieves a power efficiency of more than 90% at heavy load, and reduces the recovery time and undershoot.

Triggered by the Great East Japan Earthquake in March 2011, the authors have been studying a resilient network whose key element is a movable and deployable ICT resource unit. The resilient network needs a function of robust and immediate connection to a wide area network active outside the damaged area. This paper proposes an application of digital coherent technology for establishing optical interconnection between the movable ICT resource unit and existing network nodes through a photonic network, rapidly, easily and with the minimum in manual work. We develop a prototype of a 100Gbit/s digital coherent transponder which is installable to our movable and deployable ICT resource unit and experimentally confirm the robust and immediate connection by virtue of the plug and play function.

We investigate resolution improvement in optical quantization with keeping high sampling rate performance in optical sampling. Since our optical quantization approach uses power-to-wavelength conversion based on soliton self-frequency shift, a spectral compression can improve resolution in exchange for sampling rate degradation. In this work, we propose a different approach for resolution improvement by parallel use of dispersion devices so as to avoid sampling rate degradation. Additional use of different dispersion devices can assist the wavelength separation ability of an original dispersion device. We demonstrate the principle of resolution improvement in 3 bit optical quantization. Simulation results based on experimental evaluation of 3 bit optical quantization system shows 4 bit optical quantization is achieved by parallel use of dispersion devices in 3 bit optical quantization system. The maximum differential non-linearity (DNL) and integral non-linearity (INL) are 0.49 least significant bit (LSB) and 0.50 LSB, respectively. The effective number of bits (ENOB) estimated to 3.62 bit.

Luby Transform (LT) codes are the first practical implementation of digital fountain codes. In LT codes, encoding symbols are independently generated so as to realize the universal property which means that performance is independent of channel parameters. The universal property makes LT codes able to provide reliable delivery simultaneously via channels of different quality while it may also limit the flexibility of LT codes. In certain application scenarios, such as real-time multimedia transmission, most receivers have tolerable channels whose erasure rates are not fixed, and channels of high erasure rate are outside the design box. In this paper, Connection Choice (CC) codes are proposed to trade the universal property for better performance. The key to CC codes is replacement of random selection with tournament selection. Tournament selection can equalize the frequency of input symbols to join encoding and change the degree distribution of input symbols. Our study indicates that CC codes with appropriate degree distributions provide better performance than the best known LT code when channels of high erasure rate can be ignored. CC codes enable system designers to customize digital fountain codes by taking into account the distribution of the erasure rate and create a new possibility for setting trade-offs between performance and erasure rate.

Nonlinearity compensation algorithm and soft-decision forward error correction (FEC) are considered as key technologies for future high-capacity and long-haul optical transmission system. In this report, we experimentally demonstrate the following three benefits brought by low complexity perturbation back-propagation nonlinear compensation algorithm in 224Gb/s DP-16QAM transmission over large-Aeff pure silica core fiber; (1) improvement of pre-FEC bit error ratio, (2) reshaping noise distribution to more Gaussian, and (3) reduction of cycle slip probability.

At CaLC 2001, Howgrave-Graham proposed the polynomial time algorithm for solving univariate linear equations modulo an unknown divisor of a known composite integer, the so-called partially approximate common divisor problem. So far, two forms of multivariate generalizations of the problem have been considered in the context of cryptanalysis. The first is simultaneous modular univariate linear equations, whose polynomial time algorithm was proposed at ANTS 2012 by Cohn and Heninger. The second is modular multivariate linear equations, whose polynomial time algorithm was proposed at Asiacrypt 2008 by Herrmann and May. Both algorithms cover Howgrave-Graham's algorithm for univariate cases. On the other hand, both multivariate problems also become identical to Howgrave-Graham's problem in the asymptotic cases of root bounds. However, former algorithms do not cover Howgrave-Graham's algorithm in such cases. In this paper, we introduce the strategy for natural algorithm constructions that take into account the sizes of the root bounds. We work out the selection of polynomials in constructing lattices. Our algorithms are superior to all known attacks that solve the multivariate equations and can generalize to the case of arbitrary number of variables. Our algorithms achieve better cryptanalytic bounds for some applications that relate to RSA cryptosystems.

A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7-bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35-µm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively.

The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.

In this paper, a novel White-RGB (WRGB) color filter array-based imaging system for cell phone is presented to reduce noise and reproduce color in low illumination. The core process is based on adaptive diagonal color separation to recover color components from a white signal using diagonal reference blocks and location-based color ratio estimation in the luminance space. The experiments, which are compared with the RGB and state-of-the-art WRGB approaches, show that our imaging system performs well for various spatial frequency images and color restoration in low-light environments.

An efficient beamforming algorithm for large-scale phased arrays with lossy digital phase shifters is presented. This problem, which arises in microwave power transmission from solar power satellites, is to maximize the array gain in a desired direction with the gain loss of the phase shifters taken into account. In this paper the problem is first formulated as a discrete optimization problem, which is then decomposed into element-wise subproblems by the real rotation theorem. Based on this approach, a polynomial-time algorithm to solve the problem numerically is constructed and its effectiveness is verified by numerical simulations.

A new digital controller for a single-phase boost power factor correction (PFC) converter operating at a discontinuous conduction mode (DCM), is presented to achieve high input power factor over wide input voltage and load range. A method of duty cycle modulation is proposed to reduce the line harmonic distortion and improve the power factor. The loop regulation scheme is adopted to further improve the system stability and the power factor simultaneously. Meanwhile, a novel digital pulse width modulator (DPWM) based on the delay lock loop technique, is realized to improve the regulation linearity of duty cycle and reduce the regulation deviation. The single-phase DCM boost PFC converter with the proposed digital controller based on the field programmable gate array (FPGA) has been implemented. Experimental results indicate that the proposed digital controller can achieve high power factor more than 0.99 over wide input voltage and load range, the output voltage deviation is less than 3V, and the peak conversion efficiency is 96.2% in the case of a full load.

This paper proposes out-of-band emission reduction schemes for IEEE 802.11af based Wireless Local Area Network (WLAN) systems operating in TV White Spaces (TVWS). IEEE 802.11af adopts Orthogonal Frequency Division Multiplexing (OFDM) to exploit the TVWS spectrum effectively. The combination of the OFDM and TVWS may be able to solve the problem of frequency depletion. However the TVWS transmitter must satisfy a strict transmission spectrum mask and reduce out-of-band emission to protect the primary users. The digital convolution filter is one way of reducing the out-of-band emission. Unfortunately, implementing a strict mask needs a large number of filter taps, which causes high implementation complexity. Time-domain windowing is another effective approach. This scheme reduces out-of-band emission with low complexity but at the price of shortening the effective guard interval. This paper proposes a mechanism that jointly uses these two schemes for out-of-band emission reduction. Moreover, the appropriate windowing duration design is proposed in terms of both the out-of-band emission suppression and throughput performance for all mandatory mode of IEEE 802.11af system. The proposed time-domain windowing design reduces the number of multiplier by 96.5%.

A high-speed and low-power 8-bit subranging analog-to-digital converter (ADC) based on 65-nm CMOS technology was fabricated. Rather than using digital foreground calibration, an analog-centric approach was adopted to reduce power dissipation. An offset cancelling charge-steering amplifier and capacitive-averaging technique effectively reduce the offset, noise, and power dissipation of the ADC. Moreover, the circuit used to compensate the kickback noise current from the comparator can also reduce the power dissipation. The reference-voltage generator for the fine ADC is composed of a fine ladder and a capacitor providing an AC signal path. This configuration reduces the power dissipation of the selection signal drivers for the analog multiplexer. A test chip fabricated using 65-nm digital CMOS technology achieved a high sampling rate of 1GHz, a low power dissipation of 17.5mW, and a figure of merit of 118fJ/conv.-step.