A 4th-order programmable continuous-time filter (CTF) for hard-disk-drive (HDD) read channels was developed with 65-nm CMOS process technology. The CTF cutoff frequency and boost are programmable by switching units of the operational trans-conductance amplifier (OTA) banks and the capacitor banks. The switches are operated by lifted local-supply voltage to reduce on-resistance of the transistors. The CTF characteristics were robust against process technology variations and supply voltage and temperature ranges due to the introduction of a digitally assisted compensation scheme with analog auto-tuning circuits and digital calibration sequences. The digital calibration sequences, which fit into the operation sequence of the HDD read channel, compensate for the tuning circuits of the process technology variations, and the tuning circuits compensate for the CTF characteristics over the supply voltage and temperature ranges. As a result, the CTF had a programmability of 100–1000-MHz cutoff frequency and 0–12-dB boost.

The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.10.13 mm2.

In this letter, we describe a low power current to time converter for wireless sensor networks. The proposed circuit has some advantages of high linearity and wide measurement range. From the evaluation using HSPICE with 0.18 µm CMOS device parameters, the output differential error for the input current variation is approximately 0.1 µs/nA under the condition that the current is varied from 100 nA to 500 nA. The idle power consumption is approximately zero.

A receiver architecture and a digital IQ imbalance compensation method for dual-carrier reception are newly proposed. The impact of IQ imbalance on the baseband signal is mathematically analyzed. Based on the analysis, IQ imbalance parameters are estimated and the coupling effect of IQ imbalance is compensated using digital baseband processing alone. Simulation results show that the proposed IQ imbalance compensation successfully removes IQ imbalance. The deviation from the ideal performance is less than 1 dB when it is applied to the 3GPP-LTE carrier aggregation.

This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9 bit, 580 fs resolution in a 0.18 µm CMOS technology with 0.04 mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5 MS/s ranges from 10.8 to 12.6 mW depending on the input time intervals.

In Digital Library (DL) applications, digital book clustering is an important and urgent research task. However, it is difficult to conduct effectively because of the great length of digital books. To do the correct clustering for digital books, a novel method based on probabilistic topic model is proposed. Firstly, we build a topic model named LDAC. The main goal of LDAC topic modeling is to effectively extract topics from digital books. Subsequently, Gibbs sampling is applied for parameter inference. Once the model parameters are learned, each book is assigned to the cluster which maximizes the posterior probability. Experimental results demonstrate that our approach based on LDAC is able to achieve significant improvement as compared to the related methods.

A method of identifying JPEG 2000 images with different coding parameters, such as code-block sizes, quantization-step sizes, and resolution levels, is presented. It does not produce false-negative matches regardless of different coding parameters (compression rate, code-block size, and discrete wavelet transform (DWT) resolutions levels) or quantization step sizes. This feature is not provided by conventional methods. Moreover, the proposed approach is fast because it uses the number of zero-bit-planes that can be extracted from the JPEG 2000 codestream by only parsing the header information without embedded block coding with optimized truncation (EBCOT) decoding. The experimental results revealed the effectiveness of image identification based on the new method.

This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring oscillator. The proposed circuit monitors the PMOS and NMOS process variabilities independently according to a count number of a single pulse which propagates on the ring during the buffer ring mode, and an oscillation period during the ring oscillator mode. Using this shared-ring structure, we reduce the occupation area about 40% without loss of process variability monitoring properties compared with the conventional circuit. The proposed shared-ring circuit has been fabricated in 65 nm CMOS process and the measurement results with two different wafer lots show the feasibility of the proposed process variability monitoring scheme.

Along with the miniaturization of CMOS-LSIs, control methods for LSIs have been extensively developed. The most predominant method is to digitize observed values as early as possible and to use digital control. Thus, many types of analog-to-digital converters (ADCs) have been developed such as temperature, time, delay, and frequency converters. ADCs are the easiest circuits into which digital correction methods can be introduced because their outputs are digital. Various types of calibration method have been developed, which has markedly improved the figure of merits by alleviating margins for device variations. The above calibration and correction methods not only overcome a circuit's weak points but also give us the chance to develop quite new circuit topologies and systems. In this paper, several digital calibration and correction methods for major analog-to-digital converters are described, such as pipelined ADCs, delta-sigma ADCs, and successive approximation ADCs.

In this paper, we propose a power amplifier linearization technique combined with iterative noise cancelation. This method alleviates the effect of added noises which prevents the predistorter (PD) from estimating the exact characteristics of the power amplifier (PA). To iteratively cancel the noise added in the feedback signal, the output signal of the power amplifier without noise is reconstructed by applying the inverse characteristics of the PD to the predistorted signals. The noise can be revealed by subtracting the reconstructed signals from the feedback signals. Simulation results based on the mean-square error (MSE) and power spectral density (PSD) criteria are presented to evaluate PD performance. The results show that the iterative noise cancelation significantly enhances the MSE performance, which leads to an improvement of the out-of-band power suppression. The performance of the proposed technique is verified by computer simulation and hardware test results.

True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64–256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5 Mbps throughput.

This paper presents an ultra-wideband (UWB) bandpass filter (BPF) with sharp attenuation slope characteristics. The circuit structure consists of an inter-digital finger resonator, parallel-coupled lines and phase matching line. The design of the bandwidth was described by using the even and odd mode characteristic impedances in the resonator structure. The parallel-coupled lines were also designed in the same manner. The parameters of the resonator and two parallel-coupled lines in combination as the BPF were then optimized by the simulation with HFSS. The designed BPF was experimentally fabricated and its measured performances showed the bandwidth from 3.6 to 10 GHz with the 20 dB outband rejection. For the U.S. UWB band design, the matching line was inserted between the two parallel-coupled lines. The matching at both band edges was then qualitatively analyzed on the smithchart. The HFSS simulation results of the structure realized the bandwidth from 3.1 to 10.6 GHz with sharp attenuation slope characteristics for SWR < 2.0. The measurement results agree well with the simulation results.

Substrate noise coupling has been seriously concerned in the design of advanced analog and radio frequency (RF) integrated circuits (ICs). This paper reviews recent advancements in the modeling, analysis, and evaluation of substrate noise coupling at IC chip level. Noise generation from digital circuits and propagation to the area of analog circuits are clearly visualized both by full-chip simulation as well as by on-chip measurements, for silicon test vehicles. The impacts of substrate noise coupling are also in-depth discussed at device, circuit, as well as system levels. Overall understanding of substrate noise coupling will then provide the basics for highly reliable design of analog and RF ICs.

In this paper, a new Hammerstein predistorter modeling for power amplifier (PA) linearization is proposed. The key feature of the model is that the cubic splines, instead of conventional high-order polynomials, are utilized as the static nonlinearities due to the fact that the splines are able to represent hard nonlinearities accurately and circumvent the numerical instability problem simultaneously. Furthermore, according to the amplifier's AM/AM and AM/PM characteristics, real-valued cubic spline functions are utilized to compensate the nonlinear distortion of the amplifier and the following finite impulse response (FIR) filters are utilized to eliminate the memory effects of the amplifier. In addition, the identification algorithm of the Hammerstein predistorter is discussed. The predistorter is implemented on the indirect learning architecture, and the separable nonlinear least squares (SNLS) Levenberg-Marquardt algorithm is adopted for the sake that the separation method reduces the dimension of the nonlinear search space and thus greatly simplifies the identification procedure. However, the convergence performance of the iterative SNLS algorithm is sensitive to the initial estimation. Therefore an effective normalization strategy is presented to solve this problem. Simulation experiments were carried out on a single-carrier WCDMA signal. Results show that compared to the conventional polynomial predistorters, the proposed Hammerstein predistorter has a higher linearization performance when the PA is near saturation and has a comparable linearization performance when the PA is mildly nonlinear. Furthermore, the proposed predistorter is numerically more stable in all input back-off cases. The results also demonstrate the validity of the convergence scheme.

We propose an adaptive coding algorithm for digital hologram transmission based on server-client interaction. A client can visualize various images of 3D objects from a digital hologram, which are reconstructed on different depth planes. The client's requests for reconstruction depths are sent to the server. The server adaptively encodes and transmits the same object image as the client's reconstructed image. When the client changes the reconstruction depth, only the prediction error of the new image is transmitted. Experimental results show that, in some cases, the proposed algorithm reduces more than half of the distortion at the same bitrate compared with the conventional coding technique.

A 20 kHz audio-band ADC with a single pair of power and ground pads is implemented for a digital electret microphone. Under the limited power/ground pad condition, the switching noise effect on the signal quality is estimated via post simulations with parasitic models. Performance degradation is minimized by time-domain noise isolation with sufficient time-spacing between the sampling edge and the output transition. The prototype ADC was implemented in a 0.18 µm CMOS process. It operates under a minimum supply voltage of 1.6 V with total current of 420 µA. Operating at 2.56 MHz clock frequency, it achieves 84 dB dynamic range and a 64 dB peak signal-to-(noise+distortion) ratio. The measured power supply rejection at a 100 mVpp 217 Hz square wave is -72 dB.

The purpose of this paper is to present the static and dynamic characteristics and a smart design approach for the digital PID control forward type multiple-output dc-dc converter. The central problem of a smart design approach is how to decide the integral coefficient. Since the integral coefficient decision depends on the static characteristics, whatever integral coefficient is selected will not be yield superior dynamic characteristics. Accordingly, it is important to identify the integral coefficient that optimizes static as well as dynamic characteristics. In proposed design approach, it set the upper and lower of input voltage and output current of regulation range. The optimal integral coefficient is decided by the regulation range of the static characteristics and the dynamic characteristics and then the smart design approach is summarized. As a result, the convergence time is improved 50% compared with the conventional designed circuit.

In this paper, we propose a two-step TDC with phase-interpolator and time amplifier to satisfy high resolution at 2.4 GHz input frequency by implementing delay time less than that of an inverter delay. The accuracy of phase-interpolator is improved for process variation using the resistor automatic-tuning circuit. The gain of time amplifier is improved using the delay time difference between two delay cells. It is implemented in a 0.13 µm CMOS process with a die area of 0.68 mm2. And the power consumption is 14.4 mW at a 1.2 V supply voltage. The resolution and input frequency of the TDC are 0.357 ps and 2.4 GHz, respectively.

This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.

In this paper, a low complexity hybrid smart antenna system with directional elements and reduced-size digital beamformer is proposed to combat the inter-symbol interference (ISI) problem over frequency-selective fading channel. For the conventional smart antenna system with omni-directional elements, it utilizes the full-size digital beamformer to suppress interference and obtain the optimum performance. However, the proposed hybrid smart antenna system with directional elements can be split the linear array receiver for two branches. One branch is the subarray system with non ISI interference, which can be used for maximum ratio combiner (MRC). Another branch is the reduced-size subarray system with the ISI interference, which can use the reduced-size optimum beamformer to suppress interference. Finally, the output signals of the two branches can be combined to detect the transmitted signals. Simulation results confirm that the proposed low complexity system can provide robust performance under the multipath fading channel.