This paper presents a novel delta-sigma modulator that uses a switched-capacitor (SC) integrator with the structure of a finite impulse response (FIR) filter in a loop filter configuration. The delta-sigma analog-to-digital converter (ΔΣADC) is used in various conversion systems to enable low-power, high-accuracy conversion using oversampling and noise shaping. Increasing the gain coefficient of the integrator in the loop filter configuration of the ΔΣADC suppresses the quantization noise that occurs in the signal band. However, there is a trade-off relationship between the integrator gain coefficient and system stability. The SC integrator, which contains an FIR filter, can suppress quantization noise in the signal band without requiring an additional operational amplifier. Additionally, it can realize a higher signal-to-quantization noise ratio. In addition, the poles that are added by the FIR filter structure can improve the system's stability. It is also possible to improve the flexibility of the pole placement in the system. Therefore, a noise transfer function that does not contain a large gain peak is realized. This results in a stable system operation. This paper presents the essential design aspects of a ΔΣADC with an FIR filter. Two types of simulation results are examined for the proposed first- and second-order, and these results confirm the effectiveness of the proposed architecture.

This paper proposes a speaker-phonetic i-vector modeling method for text-dependent speaker verification with random digit strings, in which enrollment and test utterances are not of the same phrase. The core of the proposed method is making use of digit alignment information in i-vector framework. By utilizing force alignment information, verification scores of the testing trials can be computed in the fixed-phrase situation, in which the compared speech segments between the enrollment and test utterances are of the same phonetic content. Specifically, utterances are segmented into digits, then a unique phonetically-constrained i-vector extractor is applied to obtain speaker and channel variability representation for every digit segment. Probabilistic linear discriminant analysis (PLDA) and s-norm are subsequently used for channel compensation and score normalization respectively. The final score is obtained by combing the digit scores, which are computed by scoring individual digit segments of the test utterance against the corresponding ones of the enrollment. Experimental results on the Part 3 of Robust Speaker Recognition (RSR2015) database demonstrate that the proposed approach significantly outperforms GMM-UBM by 52.3% and 53.5% relative in equal error rate (EER) for male and female respectively.

An autoencoder has the potential ability to compress and decompress information. In this work, we consider the process of generating a stego-image from an original image and watermarks as compression, and the process of recovering the original image and watermarks from the stego-image as decompression. We propose embedder and extractor neural networks based on the autoencoder. The embedder network learns mapping from the DCT coefficients of the original image and a watermark to those of the stego-image. The extractor network learns mapping from the DCT coefficients of the stego-image to the watermark. Once the proposed neural network has been trained, the network can embed and extract the watermark into unlearned test images. We investigated the relation between the number of neurons and network performance by computer simulations and found that the trained neural network could provide high-quality stego-images and watermarks with few errors. We also evaluated the robustness against JPEG compression and found that, when suitable parameters were used, the watermarks were extracted with an average BER lower than 0.01 and image quality over 35 dB when the quality factor Q was over 50. We also investigated how to represent the watermarks in the stego-image by our neural network. There are two possibilities: distributed representation and sparse representation. From the results of investigation into the output of the stego layer (3rd layer), we found that the distributed representation emerged at an early learning step and then sparse representation came out at a later step.

Fail-Stop Signature (FSS) scheme is a signature scheme which satisfies unforgeability even against a forger with super-polynomial computational power (i.e. even against a forger who can compute acceptable signatures) and non-repudiability against a malicious signer with probabilistic polynomial time computational power (i.e. a PPT malicious signer). In this paper, under some settings, the equivalence relation has been derived between a set of security properties when single FSS scheme is used singly and a security property called Universally Composable (UC) security when plural FSS schemes are concurrently used. Here, UC security is a security property guaranteeing that even when plural schemes are concurrently used, security properties of each scheme (for single scheme usage) are preserved. The above main settings are as follows. Firstly, H-EUC (Externalized UC) security is introduced instead of “conventional” UC security, where a new helper functionality H is constructed appropriately. It is because that we can derive “conventional” UC security cannot hold for FSS schemes when malicious parties (e.g. a forger and a malicious signer) have super-polynomial computational power. In the environment where the above helper functionality H is used, all parties are PPT, but only a forger may compute acceptable signatures by obtaining some additional information from H. Secondly, the definition of unforgeability (in a set of security properties for single FSS scheme usage) is revised to match the above environment. The above equivalence relation derived under the above settings guarantees that even when plural FSS schemes are concurrently used, those security properties for single scheme usage are preserved, provided that some conditions hold. In particular, the equivalence relation in this paper has originality in terms of guaranteeing that unforgeability is preserved even against a forger who is PPT but may compute acceptable signatures. Furthermore, it has been firstly proved in this paper that H-EUC security holds for an existing instantiation of an FSS scheme by Mashatan et al. From this, it can be said that the equivalence relation shown in this paper is practical.

A phase locking value (PLV) in electrocorticography is an essential indicator for analysis of cognitive activities and detection of severe diseases such as seizure of epilepsy. The PLV computation requires a simultaneous pursuit of high-throughput and low-cost implementation in hardware acceleration. The PLV computation consists of bandpass filtering, Hilbert transform, and mean phase coherence (MPC) calculation. The MPC calculation includes trigonometric functions and divisions, and these calculations require a lot of computational amounts. This paper proposes an MPC calculation method that removes high-cost operations from the original MPC with mathematically identical derivations while the conventional methods sacrifice either computational accuracy or throughput. This paper also proposes a hardware implementation of MPC calculator whose latency is 21 cycles and pipeline interval is five cycles. Compared with the conventional implementation with the same standard cell library, the proposed implementation marks 2.8 times better hardware implementation efficiency that is defined as throughput per gate counts.

Bitcoin is the leading cryptocurrency in the world with a total marketcap of nearly USD 33 billion, [1] with 370,000 transactions recorded daily[2]. Pseudo-anonymous, decentralized peer-to-peer electronic cash systems such as Bitcoin have caused a paradigm shift in the way that people conduct financial transactions and purchase goods. Although cryptocurrencies enable users to securely and anonymously exchange money, they can also facilitate illegal criminal activities. Therefore, it is imperative that law enforcement agencies develop appropriate analytical processes that will allow them to identify and investigate criminal activities in the Blockchain (a distributed ledger). In this paper, INTERPOL, through the INTERPOL Global Complex for Innovation, proposes a Bitcoin analytical framework and a software system that will assist law enforcement agencies in the real-time analysis of the Blockchain while providing digital crime analysts with tracing and visualization capabilities. By doing so, it is feasible to render transactions decipherable and comprehensible for law enforcement investigators and prosecutors. The proposed solution is evaluated against three criminal case studies linked to Darknet markets, ransomware and DDoS extortion.

The authors have proposed a multi-value sequence called an NTU sequence which is generated by a trace function and the Legendre symbol over a finite field. Most of the properties for NTU sequence such as period, linear complexity, autocorrelation, and cross-correlation have been theoretically shown in our previous work. However, the distribution of digit patterns, which is one of the most important features for security applications, has not been shown yet. In this paper, the distribution has been formulated with a theoretic proof by focusing on the number of 0's contained in the digit pattern.

The main purpose of Codemark is to distribute digital contents using offline media. Due to the main purpose of Codemark, Codemark cannot be used on digital images. It has high robustness on only printed images. This paper presents a new color code called Robust Index Code (RIC for short), which has high robustness on JPEG Compression and Resize targeting digital images. RIC embeds a remote database index to digital images so that users can reach to any digital contents. Experimental results, using our implemented RIC encoder and decoder, have shown high robustness on JPEG Comp. and Resize of the proposed codemark. The embedded database indexes can be extracted 100% on compressed images to 30%. In conclusion, it is able to store all the type of digital products by embedding indexes into digital images to access database, which means it makes a Superdistribution system with digital images realized. Therefore RIC has the potential for new Internet image services, since all the images encoded by RIC are possible to access original products anywhere.

This letter describes a method that characterizes and improves the performance of a time-interleaved (TI) digital-to-analog converter (DAC) system by using multiport signal-flow graphs at microwave frequencies. A commercial signal generator with two TI DACs was characterized through s-parameter measurements and was compared to the conventional method. Moreover, prefilters were applied to correct the response, resulting in an error-vector magnitude improvement of greater than 8 dB for a 64-quadrature-amplitude-modulated signal of 4.8 Gbps. As a result, the bandwidth limitation and the complex post processing of the conventional method could be minimized.

Timing vernier (i.e., digital-to-time converter) is a key component of the pin-electronics circuit board installed in automated digital-VLSI test equipment, and it is used to create fine delays of less than one-cycle time of a clock signal. This paper presents a new on-the-fly (timing-) jitter suppression technique which makes it possible to use low-power plain-CMOS-logic-based timing verniers. Using a power-compensation line installed at the poststage of the digitally variable delay line, we make every pulse (used as a timing signal) consume a fixed amount of electric energy independent of the required delay amount. Since the power load of intrapowerlines is kept constantly, the jitter increase in the situation of changing the required delay amount on the fly is suppressed. On the basis of the concept, a 10-ns span, 125-MHz timing-vernier macro was designed and fabricated with a CMOS process for logic VLSIs. Every macro installed in a real-time timing-signal generator VLSI achieved the required timing resolution of 31.25ps with a linearity error within 15ps. The on-the-fly jitter was successfully suppressed to a random jitter level (<26ps p-p).

A new method for adaptive digital beamforming technique with compressed sensing (CS) for sparse receiving arrays with gain/phase uncertainties is presented. Because of the sparsity of the arriving signals, CS theory can be adopted to sample and recover receiving signals with less data. But due to the existence of the gain/phase uncertainties, the sparse representation of the signal is not optimal. In order to eliminating the influence of the gain/phase uncertainties to the sparse representation, most present study focus on calibrating the gain/phase uncertainties first. To overcome the effect of the gain/phase uncertainties, a new dictionary optimization method based on the total least squares (TLS) algorithm is proposed in this paper. We transfer the array signal receiving model with the gain/phase uncertainties into an EIV model, treating the gain/phase uncertainties effect as an additive error matrix. The method we proposed in this paper reconstructs the data by estimating the sparse coefficients using CS signal reconstruction algorithm and using TLS method toupdate error matrix with gain/phase uncertainties. Simulation results show that the sparse regularized total least squares algorithm can recover the receiving signals better with the effect of gain/phase uncertainties. Then adaptive digital beamforming algorithms are adopted to form antenna beam using the recovered data.

In this paper, the problem on secure communication based on chaos synchronization is investigated. The dual channel information transmitting technology is proposed to increase the security of secure communication system. Based on chaos synchronization, a new digital secure communication scheme is presented for a class of master-slave systems. Finally some numerical simulation examples are given to demonstrate the effectiveness of the given results.

Massive multiple-input multiple-output (MIMO) transmission, in which the number of antennas is considerably more than the number of user terminals, has attracted attention as a key technology in next-generation mobile communication systems, because it enables improvements in the service area and interference mitigation with simple signal processing. Multi-beam massive MIMO employing high-power beam selection in the analog part and a blind algorithm in the digital part, such as the constant modulus algorithm that does not need channel state information, has been proposed and shown to offer high transmission efficiency. In this paper, in order to realize higher transmission rates and communication efficiency, we propose a beam-selection method that uses multi-beam amplitude information only. Furthermore, this method can be realized through signal processing with a simple configuration and is highly suitable for hybrid analog-digital massive MIMO, which is advantageous in terms of cost and power consumption. Here, the effectiveness of the proposed method is verified by computer simulation.

Direct-binary search method has been used for converting complex holograms into binary format. However, this algorithm is optimized to reconstruct monochromatic digital holograms and is accurate only in a narrow-depth range. In this paper, we proposed an advanced direct-binary search method to increase the depth of field of 3D scenes reconstructed in RGB by binary holograms.

Stochastic resonance can improve the signal-to-noise ratio of digital baseband signals. However, the output of SR system needs some time for evolution to achieve global steady-state. This paper first analyzes the evolution time of SR systems, which is an important factor for digital baseband signal processing based on SR. This investigation shows that the sampling number per symbol should be rather large, and the minimum sampling number per symbol is deduced according to the evolution time of SR system.

This paper presents a fully integrated 32-MHz relaxation oscillator (ROSC) capable of sub-1-µs start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-µm CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-µs start-up time. Measured line regulation and temperature coefficient were ±0.69% and ±0.38%, respectively.

An energy efficient modulator for an ultra-low-power (ULP) 60-GHz IEEE transmitter is presented in this paper. The modulator consists of a differential duobinary coder and a semi-digital finite-impulse-response (FIR) pulse-shaping filter. By virtue of differential duobinary coding and pulse shaping, the transceiver successfully solves the adjacent-channel-power-ratio (ACPR) issue of conventional on-off-keying (OOK) transceivers. The proposed differential duobinary code adopts an over-sampling precoder, which relaxes timing requirement and reduces power consumption. The semi-digital FIR eliminates the power hungry digital multipliers and accumulators, and improves the power efficiency through optimization of filter parameters. Fabricated in a 65nm CMOS process, this modulator occupies a core area of 0.12mm2. With a throughput of 1.7Gbps/2.6Gbps, power consumption of modulator is 24.3mW/42.8mW respectively, while satisfying the IEEE 802.11ad spectrum mask.

Power amplifiers (PAs) are key components of mobile base stations. In the last decade, the power efficiency of PAs for 3G/4G mobile base stations has risen to over 50% as a result of employing efficiency enhancement techniques, such as Doherty, envelope tracking, and outphasing, in combination with GaN devices and digital predistortion. This trend has significantly contributed to reducing the power consumption of mobile base stations. Furthermore, digital transmitters using switch-mode PAs have the potential of breaking through the 70% efficiency level. Achieving this goal will require advances not only in circuitry but also in device technology. For active antenna systems of 5G mobile systems, ease of integration, as well as high efficiency, becomes important for PAs, and thus, Si-based devices will play a major role.

Block-state realization of state-space digital filters offers reduced implementation complexity relative to canonical state-space filters while filter's internal structure remains accessible. In this paper, we present a quantitative analysis on l2 coefficient sensitivity of block-state digital filters. Based on this, we develop two techniques for minimizing average l2-sensitivity subject to l2-scaling constraints. One of the techniques is based on a Lagrange function and some matrix-theoretic techniques. The other solution method converts the problem at hand into an unconstrained optimization problem which is solved by using an efficient quasi-Newton algorithm where the key gradient evaluation is done in closed-form formulas for fast and accurate execution of quasi-Newton iterations. A case study is presented to demonstrate the validity and effectiveness of the proposed techniques.

This paper proposes a method for reducing the peak-to-average power ratio (PAPR) at the output signal of a digital predistortion linearizer (DPDL) that compensates for frequency dependent intermodulation distortion (IMD) components. The proposed method controls the amplitude and phase values of the frequency components corresponding to the transmission bandwidth of the output signal. A DPDL employing the proposed method simultaneously provides IMD component cancellation of out-of-band components and PAPR reduction at the output signal. This paper identifies the amplitude and phase conditions to minimize the PAPR. Experimental results based on a 2-GHz band 1-W class power amplifier show that the proposed method improves the drain efficiency of the power amplifier when degradation is allowed in the error vector magnitude. To the best knowledge of the authors, this is the first PAPR reduction method for DPDL that reduces the PAPR while simultaneously compensating for IMD components.