This paper presents a high jitter performance injection-locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100µW power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to minimize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO's flicker noise can be suppressed, and a good PN can be achieved in flicker region (1/f3) with sub-100µW power consumption. Thus, a high figure-of-merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5/-115.3dBc/Hz at 100kHz/1MHz frequency offset with a 97µW power consumption, which corresponds to a -193/-194dBc/Hz VCO FoM at 2.62GHz oscillation frequency. The measurement results show that the 1/f3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while using a high reference clock. A 960 fs RMS jitter can be achieved with a 40MHz common reference and 107µW corresponding power.

Although transmittance changes like a quadratic function due to the DC offset voltage in FFS mode LCD, its bottom position and flicker minimum DC offset voltage varies depending on the gray level due to the flexoelectric effect. We demonstrated how the influence of the flexoelectric effect changes depending on the electrode width or black matrix position.

This paper proposes a pulse-tail-feedback VCO, in which the tail transistor is driven using pulse-shaped voltage signals with rail-to-rail swing. The proposed pulse-tail-feedback (PTFB) VCO relies on reducing the current conduction period of the tail transistor and operating the tail transistors in triode region for reducing the flicker and thermal noise from the active elements. Mathematical analysis and circuit level simulations of the phase noise mechanism in the proposed PTFB-VCO is also presented in this paper for validating the effectiveness of the proposed technique. A prototype LC-VCO with the proposed PTFB technique is fabricated in a standard 180nm CMOS. Laboratory measurement shows a power consumption of 1.35mW from a 1.2V supply at 4.6GHz. The proposed PTFB-VCO achieves a flicker corner of 700Hz, which enables the VCO to maintain a fairly constant figure-of-merit (FoM) of -195dB within a wide offset frequency range of 1kHz-10MHz.

In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H$_{2}$ annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50,nm fin width is satisfied with the requirement from 25,nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f$_{mathrm{T}}$ and f$_{mathrm{max}}$, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f$_{mathrm{T}}$ of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10,nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.

In this paper, we introduce a parallax barrier system that shows high definition autostereoscopy and holds wide viewing zone. The proposed method creates a 4-view parallax barrier system with full display resolution per view by setting aperture ratio to one quarter and using time-division quadplexing, then applies obtained 4-view to 2-view, so that the viewing zone for each eye becomes wider than that from the conventional methods. We build a prototype with two 120,Hz LCD panels and manage to achieve continuous viewing zone with common head-tracking device involved. However, moire patterns and flickers stand out, which are respectively caused by the identical alignments of the color filters on the overlaid LCD panels and a lack of refresh rate of 240,Hz. We successfully remove the moire patterns by changing the structure of the system and inserting a diffuser. We also reduce the flickers by proposing 1-pixel aperture, while stripe shaped noise due to the lack of refresh rate occurs during a blink or a saccade. The stripe noise can be effectively weakened by applying green and magenta anaglyph to the proposed system, where extra crosstalk takes place since the default RGB color filters on LCD panels share certain ranges of wavelength with each other. Although a trade-off turns out to exist between stripe noise and crosstalk from our comparison experiment, results from different settings all hold acceptable quality and show high practicability of our method. Furthermore, we propose a solution that shows possibility to satisfy both claims, where extra color filters with narrow bandwidths are required.

The effects of fluorine implantation on flicker noise and reliability of NMOSFET and PMOSFETs were concurrently investigated. The flicker noise of an NMOSFET was decreased about 66% by fluorine implantation, and that of a PMOSET was decreased about 76%. As indicated by the results, fluorine implantation is one of the methods that can be used to improve the noise characteristics of MOSFET devices. However, hot-carrier degradation was enhanced by fluorine implantation in NMOSFETs, which can be related to the difference of molecular binding within the gate oxide. On the contrary, in case of PMOSFETs, NBTI life time was increased by fluorine implantation. Therefore, concurrent investigation of hot-carrier and NBTI reliability and flicker noise is necessary in developing MOSFETs for analog/digital mixed signal applications.

The aim of this study is to improve the accuracy of flicker parameters estimation in old film sequences in which moving objects are present. Conventional methods tend to fail in flicker parameters estimation due to the effects of moving objects. Our proposed method firstly utilizes an adaptive Gaussian mixture model (GMM)-based method to detect the moving objects in the film sequences, and combines the detected results with the histogram-matched frames to generate reference frames for flicker parameters estimation. Then, on the basis of a linear flicker model, the proposed method uses an M-estimator with the reference frames to estimate the flicker parameters. Experimental results show that the proposed method can effectively improve the accuracy of flicker parameters estimation when the moving objects are present in the film sequences.

In this paper, we compare 1/f noise characteristics of High-k/Metal Gate MOSFET and SiON/Poly-Si Gate MOSFET experimentally, and evaluate the time fluctuation of drive current. These MOSFETs are fabricated with 65 nm CMOS process, and their gate lengths (Lg) are 130 nm. Specifically, we focus on the dependency of the time fluctuation of drive current on channel width (W) and temperature (T). First, we evaluate the dependency on channel width. In the case of SiON/Poly-Si Gate MOSFET, when the channel width is narrow such as W=200 nm and W=250 nm, Power Spectrum Density (PSD) depends on 1/f2 at two frequency regions. Moreover, as the channel width is wide such as W=300 nm, W=500 nm and W=1000 nm, PSD depends on 1/f and the value of PSD shifts lower. This is a new phenomena observed for the first time. On the other hand, in the case of High-k/Metal Gate MOSFET, the value of PSD is about 100 times larger than that of SiON/Poly-Si Gate MOSFET. Moreover, there is no dependency of PSD on channel width ranges from 150 nm to 1000 nm. Second, we evaluate the dependency on temperature. In the case of SiON/Poly-Si Gate MOSFET, when the temperature (T) is lowered from T=27 to T=-35, the dependency changes from the 1/f dependency to the 1/f2 dependency at two different frequency regions. This is also a new phenomena observed for the first time. However, in the case of High-k/Metal Gate MOSFET, there is no dependency of PSD on temperature ranges from 27 to -35. These results are useful knowledge for designing future LSI, because PSD dependency shows different characteristics when both channel width and temperature are changed.

An automatic and efficient algorithm for removal of intensity flicker is proposed. The novel repair process is founded on the block-based estimation and restoration algorithm with regard to luminance variation. It is easily realized and controlled to remove most intensity flicker and preserve the wanted effects, like fade in and fade out.

This paper presents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528 MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.

The pulsed backlight system has been introduced for reducing motion blurs of LCDs in high motion pictures. But applying the pulsed backlight, full screen flicker and inconsistency of transmissivity for entire frame at a lightening time should be considered. This paper discusses the analysis of blurs in high motion pictures and proposes the design method for more suitable display terminal of LCDs.

We propose a neural-sensing LSI with a bi-directional wireless interface, which is capable of detecting 5-channel neural signals in a living animal. The proposed sensing LSI consists of a multiplexer with 5-channels selectable from 10 channels, a chopper amplifier using a new direct-chopper-input scheme, a programmable multi-mode analog-to-digital converter (ADC), and a wireless-transmitter/receiver with BPSK modulation signals. The test-chip was implemented by mixed-signal 0.35-µm CMOS technology. We measured the test chip and confirmed basic operations of these blocks. The chopper-amplifier achieved 66-dB DC gain, bandwidth of 400 kHz, and 4-µV noise with power dissipation of 6-mW with a 3-V supply. We observed real nerve signals in a living cricket using the proposed chopper amplifier. ADC achieved 52-ksps operation with power dissipation of 0.43-mW at 3-V supply. The wireless transmitter achieved 1-Mbps data transmission at a distance of 1-m with 1.5-mW power dissipation at 3-V supply.

A neural-signal sensing system with multi-input-channels was designed utilizing a new chopper amplifier with direct connected to a multiplexer. The proposed system consists of multiplexers, chopper amplifiers, a multi-mode analog-to-digital converter (ADC), and a wireless transmitter. It enables to measure 50-channel signals at the same time, which are selected out of 100 channels to detect useful information. The test chip including 10-channel-inputs chopper-amplifier and multi-mode ADC, that was designed and fabricated with a mixed signal 0.35-µm CMOS technology. Utilizing the proposed direct chopper input scheme and the shared chopper amplifier, the circuits was designed with a small area of 9.4 mm2. High accuracy channel selecting and multiplexing operations were confirmed, and an equivalent input noise of 10-nV/root-Hz was obtained with test chip measurements. Power dissipation of the chopper amplifier and the ADC were 6.0-mW and 2.5-mW at a 3-V supply voltage, respectively.

The fully integrated LC voltage controlled oscillator by 0.35 µm CMOS technology is demonstrated. It has 2 GHz oscillation frequency, 23.58 mW power consumption under 3 V biased and 9.1% frequency tuning. The layout optimization method of inductor to increase quality factor and also to reduce phase noise is used. A general method is proposed which is capable of making an effective prediction of F, device excess noise number, and acquiring the phase noise of oscillators accurately. From this proposed method, the low phase noise by calculation is attained. The phase noise of measured value which shows good match with calculating data is about -115.5 dBc/Hz at off set frequency 600 kHz.

The low phase noise, low supply voltage 1.3 GHz CMOS VCO has been realized by 0.25 µm standard CMOS technology without any trimming and any tuning. The phase noise characteristics of -109 dBc/Hz and -123 dBc/Hz at 100 kHz offset and 500 kHz offset were achieved from carrier, respectively, with 1.3 GHz oscillation frequency at 1.4 V supply voltage. The performance of 1.4 V supply voltage phase noise was superior to that of 2.0 V supply voltage phase noise due to low output impedance current source. The tuning ranges of 13.3%, 16.6%, and 20.1% for 1.4 V, 1.8 V, and 2.0 V supply voltage were achieved, respectively. The amplifier consisted of one pair of PMOS differential stage with large gate length NMOS current source to realize low supply voltage operation and to avoid flicker noise contribution for phase noise. The on-chip spiral inductor consisted of three terminals arranged in a special shape to obtain high Q and small chip area. The power dissipation of this VCO was 22.4 mW without buffer amplifier.

In order to design oscillators and switches phase noise characteristic is the key to obtain high quality frequency spectrums. Since the phase noise is directly affected by the 1/f noise of transistors in the circuit, 1/f noise measurement and modeling are important. This paper describes 1/f noise measurement, frequency and bias dependent flicker noise model, and noise parameter extraction method of MOSFET's. Also, for MOSFET's geometry dependencies of drain current 1/f noise are analyzed and modeled. The model has been verified by measuring the noise current spectral density of MOSFET's in two different process devices.

For the multi-gray shades image in the passive matrix type STN-LCDs, the method which combined space modulated patterns and frame rate control(FRC)with switched some frames has been used. Although bi-level display elements are used this method makes it possible to display a multi-gray shades image without resolution-loss for still-image, while the method has a fault to perceive interference of flicker at low frame rate, as is wellknown. However the measured quantitative data for flicker and frame frequency have hardly be published. With regard to frame rate control method which some typical space modulated patterns are combined, we measure critical flicker frame frequency(CFFF) with subjective experiments. This paper also discribes that the data are arranged to be shown in form of relationship with the screen luminance and the lowest frequency components included among ripples on times and also the ripples ratio. Our experimental study provides useful data for designing such kinds of display.