We have investigated the in-situ N2-plasma nitridation for high-k HfN gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering to improve the electrical characteristics. It was found that the increase of nitridation gas pressure for the deposited HfN1.1 gate insulator, such as 98 mPa, decreased both the hysteresis width in C-V characteristics and leakage current. Furthermore, the 2-step nitiridation process with the nitridation gas pressure of 26 mPa followed by the nitridation at 98 mPa realized the decrease of equivalent oxide thickness (EOT) to 0.9 nm with decreasing the hysteresis width and leakage current. The fabricated metal-insulator-semiconductor field-effect transistor (MISFET) with 2-step nitridation showed a steep subthreshold swing of 87 mV/dec.

Enhancing the performance of low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) requires high-quality poly-Si films. One of the authors (A.H.) has already demonstrated a continuous-wave (CW) laser lateral crystallization (CLC) method to improve the crystalline quality of thin poly-Si films, using a diode-pumped solid-state CW laser. Another candidate method to increase the on-current and decrease the subthreshold swing (s.s.) is the use of a high-k gate stack. In this paper, we discuss the performance of top-gate CLC LT poly-Si TFTs with sputtering metal/hafnium oxide (HfO2) gate stacks on nonalkaline glass substrates. A mobility of 180 cm2/Vs is obtained for n-ch TFTs, which is considerably higher than those of previously reported n-ch LT poly-Si TFTs with high-k gate stacks; it is, however, lower than the one obtained with a plasma enhanced chemical vapor deposited SiO2 gate stack. For p-ch TFTs, a mobility of 92 cm2/Vs and an s.s. of 98 mV/dec were obtained. This s.s. value is smaller than the ones of the previously reported p-ch LT poly-Si TFTs with high-k gate stacks. The evaluation of a fabricated complementary metal-oxide-semiconductor inverter showed a switching threshold voltage of 0.8 V and a gain of 38 at an input voltage of 2.0 V; moreover, full swing inverter operation was successfully confirmed at the low input voltage of 1.0 V. This shows the feasibility of CLC LT poly-Si TFTs with a sputtered HfO2 gate dielectric on nonalkaline glass substrates.

The short-channel effect (SCE) in a MOSFET with an atomically thin MoS$_{2}$ channel was studied using a TCAD simulator. We derived the surface potential roll-up, drain-induced barrier lowering (DIBL), threshold voltage, and subthreshold swing (SS) as indexes of the SCE and analyzed their dependency on the channel thickness (number of atomic layers) and channel length. The minimum scalable channel length for a one-atomic-layer-thick MoS$_{2}$ MOSFET was determined from the threshold voltage roll-off to be 7.6,nm. The one-layer-thick device showed a small DIBL of 87,mV/V at a 20 nm gate length. By using high-k gate insulator, an SS lower than 70,mV/dec is achievable in sub-10-nm-scale devices.

As means to control interface reactions between HfO2 and Ge(100), chemical vapor deposition (CVD) of ultrathin Ta-rich oxide using Tri (tert-butoxy) (tert-butylimido) tantalum (Ta-TTT) on chemically-cleaned Ge(100) has been conducted prior to atomic-layer controlled CVD of HfO2 using tetrakis (ethylmethylamino) hafnium (TEMA-Hf) and O3. The XPS analysis of chemical bonding features of the samples after the post deposition N2 annealing at 300 confirms the formation of TaGexOy and the suppression of the interfacial GeO2 layer growth. The energy band structure of HfO2/TaGexOy/Ge was determined by the combination of the energy bandgaps of HfO2 and TaGexOy measured from energy loss signals of O 1s photoelectrons and from optical absorption spectra and the valence band offsets at each interface measured from valence band spectra. From the capacitance-voltage (C-V) curves of Pt-gate MIS capacitors with different HfO2 thicknesses, the thickness reduction of TaGexOy with a relative dielectric constant of 9 is a key to obtain an equivalent SiO2 thickness (EOT) below 0.7 nm.

Pentacene-based organic field-effect transistors (OFETs) with SiO2 and HfON gate insulators have been fabricated, and the effect of gate insulator on the electrical properties of pentacene-based OFETs and the microstructures of pentacene films were investigated. It was found that the grain size for pentacene film deposited on HfON gate insulator is larger than that for pentacene film deposited on SiO2 gate insulator. Due to the larger grain size, pentacene-based OFET with HfON gate insulator shows better electrical properties compared to pentacene-based OFET with SiO2 gate insulator. Meanwhile, low-temperature (such as 140) fabricated pentacene-based OFET with HfON gate insulator was also investigated. The OFET fabricated at 140 shows a small subthreshold swing of 0.14 V/decade, a large on/off current ratio of 4 104, a threshold voltage of -0.65 V, and a hole mobility of 0.33 cm2/Vs at an operating voltage of -2 V.

In this paper, we fabricated a gate-all-around bandgap-engineered (BE) silicon-oxide-nitride-oxide-silicon (SONOS) and silicon-oxide-high-k-oxide-silicon (SOHOS) flash memory device with a vertical silicon pillar type structure for a potential solution to scaling down. Silicon nitride (Si3N4) and hafnium oxide (HfO2) were used as trapping layers in the SONOS and SOHOS devices, respectively. The BE-SOHOS device has better electrical characteristics such as a lower threshold voltage (VTH) of 0.16 V, a higher gm.max of 0.593 µA/V and on/off current ratio of 5.76108, than the BE-SONOS device. The memory characteristics of the BE-SONOS device, such as program/erase speed (P/E speed), endurance, and data retention, were compared with those of the BE-SOHOS device. The measured data show that the BE-SONOS device has good memory characteristics, such as program speed and data retention. Compared with the BE-SONOS device, the erase speed is enhanced about five times in BE-SOHOS, while the program speed and data retention characteristic are slightly worse, which can be explained via the many interface traps between the trapping layer and the tunneling oxide.

As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials have attracted considerable attention. We investigated the dependence of threshold voltage (Vth) characteristics of the High-k/Metal Gate MOSFET fabricated with 65 nm CMOS process on the temperature, in comparison to conventional SiON/Poly-Si Gate MOSFET. Two aspects including the Fermi level and the channel mobility in MOSFET are discussed in details. Furthermore, the influence of threshold voltage characteristics of the High-k/Metal Gate MOSFET on the logic threshold voltage (Vth-inv) of CMOS inverter is reported in this paper.

A stacked structure consisting of ∼ 1 nm-thick MgO and ∼ 4 nm-thick HfO2 was formed on thermally grown SiO2/Si(100) by MOCVD using dipivaloymethanato (DPM) precursors, and the influences of N2 anneal on interfacial reaction and defect state density in this stacked structure were examined. The chemical bonding features of Mg atom were evaluated by using an Auger parameter independently of positive charge-up during XPS measurements. With Mg incorporation into HfO2, a slight decrease in the oxidation number of Mg was detectable. The result suggests that Mg atoms are incorporated preferentially near oxygen vacancies in the HfO2, which can be responsible for a reduction of the flat band voltage shifts observed from C-V characteristics.

A HfO2 as the charge-storage layer with the physical thickness thinner than 4 nm in silicon-oxide-high-k oxide-oxide-silicon (SOHOS) flash memory was investigated. Compared to the conventional silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, the SOHOS shows the slow operational speed and exhibits the poorer retention characteristics. These are attributed to the thin physical thickness below 4 nm and the crystallization of the HfO2 to contribute the lateral migration of the trapped charge in the trapping layer during high temperature annealing process.

In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.

HfOxNy thin films formed by the electron cyclotron resonance (ECR) Ar/N2 plasma nitridation of HfO2 films were investigated for high-k gate insulator applications. HfOxNy thin films formed by the ECR Ar/N2 plasma nitridation (60 s) of 1.5-nm-thick HfO2 films, which were deposited on chemically oxidized Si(100) substrates, were found to be effective for suppressing interfacial layer growth or crystallization during postdeposition annealing (PDA) in N2 ambient. After 900 PDA of for 5 min in N2 ambient, it was found that HfSiON film with a relatively high dielectric constant was formed on the HfOxNy/Si interface by Si diffusion. An equivalent oxide thickness (EOT) of 2.0 nm and a leakage current density of 1.010-3 A/cm2 (at VFB-1 V) were obtained. The effective mobility of the fabricated p-channel metal-insulator-semiconductor field-effect transistor (MISFET) with the HfOxNy gate insulator was 50 cm2/Vs, and the gate leakage current of the MISFET with the HfOxNy gate insulator was found to be well suppressed compared with the MISFET with the HfO2 gate insulator after 900 PDA because of the nitridation of HfO2.

We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.

We investigated the use of AlOx:N/SiNy stacked gate dielectric as an alternate gate dielectric, which were prepared by alternately repeating sub-nanometer deposition of Al2O3 from an alkylamine-stabilized AlH3 + N2O gas mixture and rapid thermal nitridation in NH3. The negative fix charges, being characteristics of almina, were as many as 3.91012 cm-2 in the effective net charge density. The effective dielectric constant and the breakdown field were 8.9 and 8 MV/cm, respectively, being almost the same as pure Al2O3. And we have demonstrated that the leakage current through the AlOx:N/SiNy stacked gate dielectric with a capacitance equivalent thickness (CET) of 1.9 nm is about two orders of magnitude less than that of thermally-grown SiO2. Also, we have confirmed the dielectric degradation similar to the stress-induced leakage current (SILC) mode and subsequent soft breakdown (SBD) reported in ultrathin SiO2 under constant current stress and a good dielectric reliability comparable to thermally-grown ultrahin SiO2. From the analysis of n+poly-Si gate metal-insulator-semiconductor field effect transistor (MISFET) performance, remote coulomb scattering due to changes in the gate dielectric plays an important role on the mobility degradation of MISFET with AlON/SiON gate stack.

A new sputtering technique named "itshape limited reaction sputtering" is proposed and the feasibility toward an ultra-thin gate insulator is investigated. 5-10 nm thick ZrO2 films were prepared on Si(100) substrates and analyzed by XPS, HR-RBS and RHEED. Significant Zr diffusion into the Si substrate and interface oxidation were not observed. An optimum film was obtained at growth temperature of 300, oxygen flow rate of 4.2% and 500-10 sec RTA. The equivalent oxide thickness of 2 nm was realized with leakage current of 10-7 A/cm2 at 1.5 MV/cm.

Though, high dielectric constant material is a possible near future solution in order to suppress gate current densities of MOSFETs, the barrier height generally decreases with an increasing dielectric constant. In this paper, the injection current through gate stacks has been calculated while taking into account the electron temperature using the W.K.B. method to understand the impact of the injection current from the drain edge.