A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

A full CMOS cell technology for high density SRAMs has been developed. A 0.4 µm n+/p+ spacing has been achieved by a shallow trench isolation with a retrograde and a shallow well design. Dual gate 0.35 µm n- and p-channel MOSFETs were used for the high density full CMOS SRAM cell. The side-wall inversion problem to which MOSFETs are subject due to the trench isolation structure has been controlled by combining taper angled trench etching and a rounded trench edge shape. A dual gate 0.4 µm nMOS/pMOS spacing has also been accomplished with no lateral gate dopant diffusion by an enlarged grain size tungsten polycide gate structure. These techniques can resolve the bottleneck problem of full CMOS SRAM cell size reduction, and realize a competitive cell size against conventional polysilicon resistor load SRAM cell (E/R type cell) or thin-film-transistor load SRAM cell (TFT type cell) structures. A test chip of a 256 k bit full CMOS SRAM was fabricated to verify the process integration of the shallow trench isolation with the retrograde shallow well design and the dual gate CMOS structure. It has been recognized that the above techniques are possible solutions for deep sub-micron high density full CMOS SRAM cell structure.

A novel isolation structure which has a buried insulator between polysilicon electrodes (BIPS) has been developed. The BIPS isolation employs the refilling CVD-oxides in openings between polysilicon electrodes by photoresist etchback process. Device characteristics and parasitic effects of BIPS isolation have been compared with that of LOCOS isolation. Using BIPS isolation, we can almost suppress the narrow-channel effects and achieve the deep submicron isolation. No degradation on the subthreshold decay of devices with BIPS isolation can be obtained. The use of BIPS isolation technology yields a DRAM cell of small area. The successful fabrication of deep submicron devices with BIPS isolation clearly demonstrates that this technology has superior ability to overcome the LOCOS isolation.

Junction leakage current of trench isolation devices is strongly influenced by trench configuration. The origin of the leakage current is the mechanical stress that is generated by the differential thermal expansion between the Si substrate and the SiO2 filled isolation trench during the isolation forming process. A two-dimensional mechanical stress simulation was used to analyze trench-isolated devices. The simulated distribution and magnitude of stress were found to agree with Raman spectroscopic measurements of actual devices. The stress in the deeper regions between deep trenches is likely to increase greatly as the size of devices diminishes, so it is important to reduce this stress and thus suppress junction leakage current.

A two-dimensional photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices with channel width ranging from 160 µm to 0.2 µm is described. Photoemission-intensity profiles can be measured in spatial resolution of 0.1 µm. Different photoemission characteristics are observed in n-MOSFETs depending on isolation technology; M-shaped photoemission-intensity profiles are observed as gate voltage becomes higher in trench-isolated ones, but scarcely measured in LOCOS-isolated ones. As for p-MOSFETs, similar characteristics are observed independent on isolation technology and slightly M-shaped profiles are observed at higher gate voltages. The recession of 0.1-0.2 µm in photoemission area from the gate electrode edge due to gate bias dependence of the pinch-off points of n--LDD drain is observed when gate voltage increases from 1 V to 6 V. Meanwhile the recession of the pinch-off points in p-MOSFETs is less than 0.1 µm even when gate voltage increases from 2 V to 8 V. A qualitative explanation for the experimental results is given for four kinds of MOSFETs in comparing each device structure near the isolation edge.

Localized temperature distribution in silicon on insulator (SOI) structures with trench isolations is calculated using three-dimensional computer simulation. Temperature rise in SOI transistors is about three times higher than in conventional structure transistors because the thermal conductivity of SiO2 is very low. If there are voids in the SiO2 layers and trench isolations, temperature in the SOI transistors increases significantly. A simple model is proposed to calculate steady-state temperature rise in SOI transistors.

Isolation characteristics, which are important factors in designing GaAs ICs, are investigated focusing on leak current between circuit elements on a semi-insulating substrate and on the sidegating effect that results from leak current between MESFETs. We have found that the large leak current comes from the projecting edge, located outside the channel, of the gate electrode and that this leak current is the main cause of the sidegating effect. By taking into account quantitatively evaluated isolation characteristics, we can improve LSI design rules to reproducible and reliable operation.

A new channel stop design for submicton local oxidation of silicon (LOCOS) isolation was presented. The n-channel stop was designed with boron implanation after forming LOCOS, while the p-channel stop was constructed with high energy phosphorus or arsenic implantation before or after forming LOCOS. These optimized channel stop designs can extend an isolation spacing to the submicron region without a decrease in junction breakdown voltage and an increase in junction leakage current. Narrow channel effects were found to be effectively suppressed by optimum channel stop design issues.