The investigation of device functions required from the systems point of view will be important for the development of the next generation of VLSI devices and systems. In this paper, a super pass transistor (SPT) model is presented as a quantum device candidate for future VLSI systems based on multiple-valued logic. A possible quantum device structure for the SPT model is also described, which employs the concepts of a lateral-resonant-tunneling quantum-dot transistor and a heterostructure field-effect transistor. Since it has the powerful capability of detecting multiple signal levels, the SPT will be useful for the implementation of highly compact multiple-valued VLSI systems. To exploit the functionality of the SPT, a super pass gate (SP-gate) corresponding to a single SPT is proposed as a multiple-valued universal logic module. The mathematical properties of the SP-gate are discussed. A design method for a multiple-valued SP-gate network is presented. An application of SP-gates to a multiple-valued image processing system is also demonstrated. The SP-gate network for the multiple-valued image processing system is evaluated in comparison with the corresponding NMOS implementation in terms of the number of transistors, interconnections and cascaded transistor stages. The size of a generalized series-parallel SP-gate network is also evaluated in comparison with a functionally equivalent multiple-valued series-parallel MOS pass transistor network. The results show that highly compact multiple-valued VLSI systems can be achieved if the SPT-model can be realized by an actual quantum device.

In this paper, we propose a method to design ternary cellular arrays by using Ternary Decision Diagrams (TDD's). Our cellular array has a rectangular structure composed of ternary switch cells. The ternary functions represented by TDD's are realized by mapping the TDD's to the arrays directly. That is, both the nodes and the edges in the TDD are realized by some sets of the cells. Since TDD's can represent easily multiple-output functions without large memory requirements, our arrays are wuitable for the realization of multiple-output functions. To evaluate our method, we apply our method to some benchmark circuits, and compare our arrays with the ternary PLA's. The experimental results show that our arrays have the advantage for their sizes, especially in the realization of symmetric functions. The results also clarify that the size of our arrays depends on the size of TDD's.

This paper presents a novel and successful logic synthesis method for optimizing ternary logic functions of any given number of input variables. A new optimization algorithm to synthesize and minimize an arbitrary ternary logic function of n-input variables can always lead this function to optimal or very close to optimal solution, where [n (n1)/2]1 searches are necessary to achieve the optimal solution. Therefore, the complexity number of this algorithm has been greatly reduced from O(3n) into O(n2). The advantages of this synthesis and optimization algorithm are: (1) Very easy logic synthesis method. (2) Algorithm complexity is O(n2). (3) Optimal solution can be obtained in very short time. (4) The method can solve the interconnection problems (interconnection delay) of VLSI and ULSI processors, where very fast and parallel operations can be achieved. A transformation method between operational and polynomial domains of ternary logic functions of n-input variables is also discussed. This transformation method is very effective and simple. Design of the circuits of GF(3) operators, addition and multiplication mod-3, have been proposed, where these circuits are composed of Josephson junction devices. The simulation results of these circuits and examples show the following advantages: very good performances, very low power consumption, and ultra high speed switching operation.

In this paper, a fault model for multiple-valued programmable logic arrays (MV-PLAs) is proposed and the equivalences of faults of MV-PLA's are discussed. In a supposed multiple-valued NOR/TSUM PLA model, it is shown that multiple-valued stuck-at faults, multiple-valued bridging faults, multiple-valued threshold shift faults and other some faults in a literal generator circuit are equivalent or subequivalent to a multiple crosspoint fault in the NOR plane or a multiple fault of weights in the TSUM plane. These results lead the fact that multiple-valued test vector set which indicates all multiple crosspoint fault and all multiple fault of weights also detects above equivalent or subequivalent faults in a MV-PLA.

This paper proposes a repairable and diagnosable k-valued cellular array. We assume a single fault, i.e., either stuck-at-O fault or stuck-at-(k1) fault of switches occurs in the array. By building in a duplicate column iteratively, when a stuck-at-(k1) fault occurs in the array, the fault never influences the output of the array. That is, we can construct a fault-tolerant array for the stuck-at-(k1) fault. While, for the stuck-at-O fault, the diagnosing method is simple and easy because we don't have to diagnose the stuck-at-(k1) fault. Moreover, our array can be repaired easily for the fault. The comparison with other rectangular arrays shows that our array has advantages for the number of cells and the cost of the fault diagnosis.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.

Truncated sum (TSUM for short) is useful for MV-PLA's realization. This paper introduces a new class of multiple-valued logic functions that are expressed by truncated sum, differential product (DPRODUCT for short), NOT and variables, where TSUM (x, y)min (xy, p1) and DPRODUCT (x, y)max (xy(p1), 0) is newly defined as the product that is derived by applying De Morgan's laws to TSUM. We call the functions T-functios. First, this paper clarifies that a set of T-functions is not a lattice. It clarifies that Lukasiewicz implication can be expressed by TSUM and NOT. It guarantees that a set of p-valued T-functios is not complete but complete with constants. Next, the speculations of the number of T-functions for less than ten radixes are derived. For eleven or more radix p, a speculation of the number of p-valued T-functions is shown. Moreover, it compares the T-functions with B-functions. The B-functions have been defined as the functions expressed by MAX, MIN, NOT and variables. As a result, it shows that a set of T-functions includes a set of B-functions. Finally, an inclusion relation among these functional sets and normality condition is shown.

A new multiple-valued mask-ROM cell and a technique suitable for data detection are proposed. The information is programmed in each of the memory cells as both the threshold voltage and the channel length of the memory cell transistor, and the stored data are detected by selecting the bias condition of both the word-line and the data-line. The datum stored in the channel length is read-out using punch-through effect at the high drain voltage. The feasibility of this mask-ROM's is studied with device simulation and circuit simulation. With this design, it would be possible to get the high-density mask-ROM's, which might be faster in access speed and easier in fabrication process than the conventional ones. Therefore, this design is expected to be one of the most practical multiple-valued mask-ROM's.

This paper presents a high-density multiple-valued content-addressable memory (MVCAM) based on a floating-gate MOS device. In the proposed CAM, a basic operation performed in each cell is a threshold function that is a kind of inverter whose threshold value is programmable. Various multiple-valued operations for data retrieval can be easily performed using threshold functions. Moreover, each cell circuit in the MVCAM can be implemented using only a single floating-gate MOS transistor. As a result, the cell area of the four-valued CAM are reduced to 37% in comparison with that of the conventional dynamic CAM cell.

A new arithmetic multiple-valued algebra with functional completeness is introduced. The algebra is called Neuro-Algebra for it has very similar formula and architecture to neural networks. Two canonical forms of multiple-valued functions of this Neuro-Algebra are presented. Since the arithmetic operations of the Neuro-Aglebra are basically a weighted-sum and a piecewise linear operations, their implementations are very simple and straightforward. Furthermore, the multiple-valued networks based on the Neuro-Algebra can be trained by the traditional back-propagation learning algorithm directly.

A new circuit design of Josephson ternary δ-gate composed of Josephson junction devices is presented. Mathematical theory for synthesizing, analyzing, and realizing any given function in ternary system using Josephson ternary δ-gate is introduced. The Josephson ternary δ-gate is realized using SQUID technique. Circuit simulation results using J-SPICE demonstrated the feasibility and the reliability operations of Josephson ternary δ-gate with very high performances for both speed and power consumption (max. propagation delay time44 ps and max. power consumption2.6µW). The Josephson ternary δ-gate forms a complete set (completeness) with the ternary constants (1, 0, 1). The number of SQUIDs that are needed to perform the operation of δ-gate is 6. Different design with less than 6 SQUIDs is not possible because it can not perform the operation of δ-gate. The advantages of Josephson ternary δ-gate compared with different Josephson logic circuits are as follows: The δ-gate has the property that a simple realization to any given ternary logic function as the building blocks can be achieved. The δ-gate has simple construction with small number of SQUIDs. The δ-gate can realize a large number of ternary functions with small number of input/output pins. The performances of δ-gate is very high, very low power consumption and ultra high speed switching operation.

Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

This paper proposes new architecture LSIs based on wave-parallel computing to provide an essential solution to the interconnection problems in massively parallel processing. The basic concept is ferquency multiplexing of digital information, which enables us to utilize the parallelism of electrical (or optical) waves for parallel processing. This wave-parallel computing concept is capable of performing several independent binary funtions in parallel with a single module. In this paper, we discuss the design of wave-parallel image processing LSI to demonstrate the feasibility of reducing the number of interconnections among modules.

Recently, fuzzy logic which is a kind of infinite multiple-valued logic has been studied to treat certain ambiguities, and its algebraic properties have been studied by the name of fuzzy logic functions. In order to treat modality (necessity, possibility) in fuzzy logic, which is an important concept of multiple-valued logic, the intuitionistic logical negation is required in addition to operations of fuzzy logic. Infinite multiple-valued logic functions introducing the intuitionistic logical negation into fuzzy logic functions are called Kleene-Stone logic functions, and they enable us to treat modality. The domain of modality in which Kleene-Stone logic functions can handle, however, is too limited. We will define α-KS logic functions as infinite multiple-valued logic functions using a unary operation instead of the intuitionistic logical negation of Kleene-Stone logic functions. In α-KS logic functions, modality is closer to our feelings. In this paper we will show some algebraic properties of α-KS logic functions. In particular we prove that any n-variable α-KS logic function is determined uniquely by all inputs of 7 values which are 7 specific truth values of the original infinite truth values. This means that there is a bijection between the set of α-KS logic functions and the set of 7-valued α-KS logic functions which are restriction of α-KS logic functions to 7 specific truth values. Finally, we show a necessary and sufficient condition for a 7-valued logic function to be a 7-valued α-KS logic function.

A new computer architecture using multiwavelength optoelectronic integrated circuits (OEICs) is proposed to attack the problems caused by interconnection complexity. Multiwavelength-OEIC architecures, where various wavelengths are employed as information carriers, provide the wavelength as an extra dimension of freedom for parallel processing, so that we can perform several independent computations in parallel in a single optical module using the wavelength space. This multiplex computing" enables us to reduce the wiring area required by a network and improve their complexity. In this paper, we discuss the efficient multiplexing of Batcher's bitonic sorting networks, highly parallel computing architectures that require global interconnections inherently. A systematic multiplexing of interconnection topology is presented using a binary representation of the connectivities of interconnection paths. It is shown that the wiring area can be reduced by a factor of 1/r2 using r kinds of wavelength components.

This paper presents Bi-CMOS current-mode multiple valued logic circuit with 1.5 V supply voltage. This circuit is composed of current mirror, threshold detector and current source. This circuit has advantages such as high accuracy, high speed, high density and low supply voltage. So, it is possible to realize high-radix multiple valued logic circuit. As an other application of the proposed circuit, a processing unit of fuzzy inference is given. This circuit operates with high speed and high accuracy. The circuit simulation of the proposed circuit has been performed using SPICE2 program.

An idea of optimal output permutation of multiple-valued sum-of-products expressions is presented. The sum-of-products involve the TSUM operator on the MIN of window literal functions. Some bounds on the maximum number of implicants needed to cover an output permuted function are clarified. One-variable output permuted functions require at most p1 implicants in their minimal sum-of-products expressions, where p is the radix. Two-variable functions with radix between three and six are analyzed. Some speculations of maximum number of the implicants could be established for functions with higher radix and more than 2-variables. The result of computer simulation shows that we can have a saving of approximately 15% on the average using permuting output values. Moreover, we demonstrate the output permutation based on the output density as a simpler method. For the permutation, some speculation is shown and the computer simulation shows a saving of approximately 10% on the average.

Design of locally computable combinational circuits is a very important subject to implement high-speed compact arithmetic and logic circuits in VLSI systems. This paper describes a multiple-valued code assignment algorithm for the locally computable combinational circuits, when a functional specification for a unary operation is given by the mapping relationship between input and output symbols. Partition theory usually used in the design of sequential circuits is effectively employed for the fast search for the code assignment problem. Based on the partition theory, mathematical foundation is derived for the locally computable circuit design. Moreover, for permutation operations, we propose an efficient code assignment algorithm based on closed chain sets to reduce the number of combinations in search procedure. Some examples are shown to demonstrate the usefulness of the algorithm.