In this paper, a new transceiver system for the in-vehicle communication system is proposed to enhance data transmission rate and timing accuracy in TDM-based application. The proposed system utilizes point-to-point (P2P) channel, a closed-loop clock forwarding path, and a transceiver with a repeater and clock delay adjuster. The proposed system with 4 ECU (Electronic Computing Unit) nodes is implemented in 180nm CMOS technology and, when compared with conventional bus-based system, achieved more than 125 times faster data transmission. The maximum data rate was 2.5Gbps at 1.8V power supply and the worst peak-to-peak jitter for the data and clock signals over 5000 data symbols were about 49.6ps and 9.8ps respectively.

This paper describes the results of outdoor mobility measurements and high-speed vehicle tests that clarify the 4-by-8 multiple-input multiple-output (MIMO) throughput performance when applying distributed MIMO with narrow antenna-beam tracking in a 28-GHz frequency band in the downlink of a 5G cellular radio access system. To clarify suitable transmission point (TP) deployment for mobile stations (MS) moving at high speed, we examine two arrangements for 3TPs. The first sets all TPs in a line along the same side of the path traversed by the MS, and the other sets one TP on the other side of the path. The experiments in which the MS is installed on a moving wagon reveal that the latter deployment case enables a high peak data rate and high average throughput performance exhibiting the peak throughput of 15Gbps at the vehicle speed of 3km/h. Setting the MS in a vehicle travelling at 30km/h yielded the peak throughput of 13Gbps. The peak throughput of 11Gbps is achieved at the vehicle speed of 100km/h, and beam tracking and intra-baseband unit hand over operation are successfully demonstrated even at this high vehicle speed.

Break arcs are generated in a 48VDC resistive circuit. Circuit current I0 when electrical contacts are closed is changed from 50A to 300A. The break arcs are observed by a high-speed camera with appropriate settings of exposure from horizontal direction. Length of the break arcs L is measured from images of the break arcs. Time evolutions of the length L and gap voltage Vg are investigated. The following results are obtained. By appropriate settings of the high-speed camera, the time evolution of the length L is obtained from just after ignition to before arc extinction. Tendency of increase of the length L is similar to that of increase of the voltage Vg for each current I0.

Data rate requirements, from consumer application to automotive and aerospace grew rapidly in the last years. This led to the development of a series of communication protocols (i.e. Ethernet, PCI-Express, RapidIO and SpaceFibre), which use more than one communication lane, both to speed up data rate and to increase link reliability. Some of these protocols, such as SpaceFibre, are able to detect real-time changes in the number of active lanes and to adapt the data flow appropriately, providing a flexible solution, robust to lane failures. This results in a real time varying data path in the lower layers of the data handling system. The aim of this paper is to propose the architecture of a hardware block capable of reading a fixed number of words from a host FIFO and shaping them on a real time variable number of words equal to the number of active lanes.

A novel image enhancement method for vein recognition is introduced. Inspired by observation that the intensity of the vein vessel changes rapidly during the smoothing process compared to that of background (i.e., skin tissue) due to its thin and long shape, we propose to exploit the smoothing speed as a restoration weight for the vein image enhancement. Experimental results based on the CASIA multispectral palm vein database demonstrate that the proposed method is effective to improve the performance of vein recognition.

Many applications, such as image signal processing, has an inherent tolerance for insignificant inaccuracies. Multiplication is a key arithmetic function for many applications. Approximate multipliers are considered an efficient technique to trade off energy relative to performance and accuracy for the error-tolerant applications. Here, we design and analyze four approximate multipliers that demonstrate lower power consumption and shorter critical path delay than the conventional multiplier. They employ an approximate tree compressor that halves the height of the partial product tree and generates a vector to compensate accuracy. Compared with the conventional Wallace tree multiplier, one of the evaluated 8-bit approximate multipliers reduces power consumption and critical path delay by 36.9% and 38.9%, respectively. With a 0.25% normalized mean error distance, the silicon area required to implement the multiplier is reduced by 50.3%. Our multipliers outperform the previously proposed approximate multipliers relative to power consumption, critical path delay, and design area. Results from two image processing applications also demonstrate that the qualities of the images processed by our multipliers are sufficiently accurate for such error-tolerant applications.

Dual-rotor machine (DRM) is a multiple input and output electromechanical device with two electrical and two mechanical ports which make it an optimal transmission system for hybrid electric vehicles. In attempt to boost its performance and efficiency, this work presents a dual-rotor permanent magnet (DR-PM) machine system used for continuously variable transmission (CVT) in HEVs. The proposed DR-PM machine is analyzed, and modeled in consideration of vehicle driving requirements. Considering energy conversion modes and torque transfer modes, operation conditions of the DR-PM machine system used for CVT are illustrated in detail. Integrated control model of the system is carried out, besides, intelligent speed ratio control strategy is designed by analyzing the dynamic coupling modes upon the integrated models to satisfy the performance requirements, reasonable energy-split between machine and engine, and optimal fuel economy. Experimental results confirm the validity of the mathematical model of the DR-PM machine system in the application of CVT, and the effectiveness of the intelligent speed ratio control strategy.

It is a hot issue that speeding up the network layers and decreasing the network parameters in convolutional neural networks (CNNs). In this paper, we propose a novel method, namely, symmetric decomposition of convolution kernels (SDKs). It symmetrically separates k×k convolution kernels into (k×1 and 1×k) or (1×k and k×1) kernels. We conduct the comparison experiments of the network models designed by SDKs on MNIST and CIFAR-10 datasets. Compared with the corresponding CNNs, we obtain good recognition performance, with 1.1×-1.5× speedup and more than 30% reduction of network parameters. The experimental results indicate our method is useful and effective for CNNs in practice, in terms of speedup performance and reduction of parameters.

Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes an accuracy-controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. An 8×8 multiplier design is implemented by employing the carry-maskable adder and the compressor. Compared with a conventional Wallace tree multiplier, the proposed multiplier reduced power consumption by between 47.3% and 56.2% and critical path delay by between 29.9% and 60.5%, depending on the required accuracy. Its silicon area was also 44.6% smaller. In addition, results from two image processing applications demonstrate that the quality of the processed images can be controlled by the proposed multiplier design.

In this paper, the analog code modulation characteristics of distributed-based transversal filters (DTFs) suitable for use in spectrally encoded CDMA systems are presented. The DTF is verified as an appropriate method to use in high-speed CDMA systems as opposed to previously proposed methods, which are intended for Direct Sequence (DS) CDMA systems. The large degree of freedom of DTF design permits controlling the filter pulse response to generate well specified temporal phase-coded signals. A decoder structure that performs bipolar detection of user subbands giving rise to a Spectral-Amplitude Encoded CDMA system is considered. Practical implementations require truncating the spreading signals by a time window of duration equal to the span time of the tapped delay line. Filter functions are chosen to demodulate the matched channel and achieve improved user interference rejection avoiding the need for transversal filters featuring a large number of taps. As a proof-of-concept of the electronic SAE scheme, practical circuit designs are developed at low speeds (3-dB point at 1 GHz) demonstrating the viability of the proposal.

Electrical contacts are separated at constant speed and break arcs are generated in nitrogen or air in a 200V-450VDC/10A resistive circuit. The break arcs are extinguished by magnetic blow-out. Arc duration for the silver and copper contact pairs is investigated for each supply voltage. Following results are shown. The arc duration for Cu contacts in nitrogen is the shortest. For Cu contacts, the arc dwell time in air was considerably longer than that of nitrogen. For Ag contacts, the arc duration in nitrogen was almost the same as that in air.

A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s·2(SFDR/6)/W. A proof-of-concept chip with an active area of only 0.22mm2 was measured in prototypes encapsulated in a 144-pins low profile quad flat package.

This paper proposes and analyzes a pipelining scheme for a hardware squarer that can square unsigned integers of up to 12 bits. Each stage is designed and adjusted such that stage delays are well balanced and that the critical path delay of the design does not exceed the reference value which is set up based on the analysis. The resultant design has the critical path delay of approximately 3.5 times a full-adder delay. In an implementation using an Intel Stratix V FPGA, the design operates at approximately 23% higher frequency than the comparable pipelined squarer provided in the Intel library.

In this paper, a weighted multiple bit flipping (WMBF) algorithman for decoding low-density parity-check (LDPC) codes is proposed first. Then the improved WMBF algorithm which we call the efficient weighted bit-flipping (EWBF) algorithm is developed. The EWBF algorithm can dynamically choose either multiple bit-flipping or single bit-flipping in each iteration according to the log-likelihood ratio of the error probability of the received bits. Thus, it can efficiently increase the convergence speed of decoding and prevent the decoding process from falling into loop traps. Compared with the parallel weighted bit-flipping (PWBF) algorithm, the EWBF algorithm can achieve significantly lower computational complexity without performance degradation when the Euclidean geometry (EG)-LDPC codes are decoded. Furthermore, the flipping criterion does not require any parameter adjustment.

Arc runners are fixed on silver electrical contacts. Break arcs are generated between the contacts in a 450VDC circuit. Break arcs are magnetically blown-out and air is blown to the break arcs. The air flow was not used to our previous reports with runners. Circuit current when contacts are closed is 10A. Flow rate of air Q is changed from 1 to 10L/min. Supply voltage E is changed from 200V to 450V. The following results are shown. Arc duration D tends to decrease with increasing flow rate Q. The number of reignitions N increases with increasing supply voltage E for each flow rate Q. The number of reignitions is the least when the flow rate Q is 2L/min.

Break arcs are rotated with a radial magnetic field formed by a permanent magnet embedded in a fixed contact. The break arcs are generated in a 48VDC resistive circuit. The circuit current is 10A when the contacts are closed. The polarity of the fixed contact in which the magnet is embedded is changed. The rotational radius and the difference of position between the cathode and anode spots are investigated. The following results are obtained. The cathode spot is moved more easily than the anode spot by the radial magnetic field. The rotational radius of the break arcs is affected by the Lorentz force that is caused by the circumferential component of the arc current and the axial component of the magnetic field. The circumferential component of the arc current is caused by the difference of the positions of the rotating cathode and anode spots.

This paper reviews long optical reach and large capacity transmission which has become possible because of the application of wide-band and low-noise optical fiber amplifiers and digital coherent signal processing. The device structure and mechanism together with their significance are discussed.

The growing demand for high-speed data communication has continued to meet the need for ever-increasing I/O bandwidth in recent VLSI systems. However, signal integrity issues, such as intersymbol interference (ISI) and reflections, make the channel band-limited at high-speed data rates. We propose high-speed data transmission techniques for VLSI systems using Tomlinson-Harashima precoding (THP). Because THP can eliminate ISI by inverting the characteristics of channels with limited peak and average power at the transmitter, it is suitable for implementing advanced low-voltage and high-speed VLSI systems. This paper presents a novel double-rate THP equalization technique especially intended for multi-valued data transmission to further improve THP performance. Simulation and measurement results show that the proposed THP equalization with a double sampling rate can enhance the data transition time and, therefore, improve the eye opening.

Improved fractional variable tap-length adaptive algorithm that contains Sigmoid limited fluctuation function and adaptive variable step-size of tap-length based on fragment-full error is presented. The proposed algorithm can solve many deficiencies in previous algorithm, comprising small convergence rate and weak anti-interference ability. The parameters are able to modify reasonably on the basis of different situations. The Sigmoid constrained function can decrease the fluctuant amplitude of the instantaneous errors effectively and improves the ability of anti-noise interference. Simulations demonstrate that the proposed algorithm equips better performance.

In this paper, we propose an algorithm that enhances the number of pixels for high-speed imaging. High-speed cameras have a principle problem that the number of pixels reduces when the number of frames per second (fps) increases. To enhance the number of pixels, we suppose an optical structure that block-randomly selects some percent of pixels in an image. Then, we need to reconstruct the entire image. For this, a state-of-the-art method takes three-dimensional reconstruction strategy, which requires a heavy computational cost in terms of time. To reduce the cost, the proposed method reconstructs the entire image frame-by-frame using a new cost function exploiting two types of sparsity. One is within each frame and the other is induced from the similarity between adjacent frames. The latter further means not only in the image domain, but also in a sparsifying transformed domain. Since the cost function we define is convex, we can find the optimal solution using a convex optimization technique with small computational cost. We conducted simulations using grayscale image sequences. The results show that the proposed method produces a sequence, mostly the same quality as the state-of-the-art method, with dramatically less computational time.