We present a new framework for checking safety failures. The approach is based on the conservative inference of the internal states of a system by the observation of the interaction with its environment. It is based on two similar mechanisms : forward implication, which performs the analysis of the consequences of an input applied to the system, and backward implication, that performs the same task for an output transition. While being a very simple approach, it is general and we believe it can yield efficient algorithms in different safety-failure checking problems. As a case study, we have applied this framework to an existing problem, the hazard checking in (speed-independent) asynchronous circuits. Our new methodology yields an efficient algorithm that performs better or as well as all existing algorithms, while being more general than the fastest one.

In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220 MHz at 1.6 GS/s, and almost five effective bits for 660 MHz input at 1.6 GS/s. Peak INL and DNL are less than 0.5 LSB and 0.45 LSB, respectively. This ADC consumes 85 mW from 1.8 V at 1.6 GS/s and occupies an active area of 0.27 mm2. It is fabricated in 0.18-µm CMOS.

In conventional road-vehicle communication systems, user terminals in the vehicles have to directly connect to wireless access points (APs). However, vehicle speeds are so fast that the channel condition between the terminals and the APs constantly changes because of changing path loss and time-varying fading. In this paper, to compensate for such deterioration, we propose to reduce the relative speed between the terminals and the APs by an inter-vehicle packet relay technique. If a terminal can send data via other vehicles running at lower speeds, the relative speed will decrease, which suppresses the dynamic range of path loss and deterioration by fading. We, first, validate our method by a numerical analysis using a statistical path-loss model. The numerical analysis verifies that our method is able to suppress deterioration caused by path loss and time-varying fading. However, in the numerical analysis, geometric propagation of paths is not considered; instantaneous and rapid loss changes are not considered. Therefore, we evaluate our method by computer simulations using a geometric propagation model. In the simulations, phase difference between multiple paths and loss fluctuation within one frame duration affect the performance. From the results of the simulations, we validate our method. Furthermore, we investigate the combination of our method and the selection diversity technique, which can suppress channel fluctuation and may enhance the performance of our method. Moreover, we measure interference in the overlapped zone between two AP areas. From the measurement, we show that our packet relays do not cause a problem in interference between areas.

A new level shifter is proposed in this paper that mitigates the contention problem between its pull-up and pull-down switches without suffering the delay penalty. Comparing this new one with two conventional shifters (CLS-1 and CLS-2) indicates that CLS-1 and CLS-2 have the delay times which are 308% and 26% slower than the proposed shifter when VDDL/VDDH=0.3 and the fan-out=2, respectively. In addition, the comparison of power-delay products shows CLS-2 consumes 28.5% more energy than the proposed shifter. For the layout area, the proposed shifter needs only 15% more than CLS-2. By comparing the propagation delay times, the power-delay products, and the area overhead, the proposed shifter is considered very suitable to future Very Deep Sub-Micron (VDSM) technologies with low-voltage applications.

The possibility of using three kinds of new type composite materials as material for high speed sliding contacts was investigated. The results of this investigation were compared with the results of the low speed tests that were reported earlier. As a result of the above, it was discovered that for high speed rotation in the range from 0.014 m/s to 2 m/s, the order of merit did not significantly change. Based on this, it was concluded that if solid lubricant is effectively supplied to the sliding surface, the influence by frictional heat generated by high speed is slight. Of the three kinds of composite material, it was clarified that composite material (CMML-1) had the lowest contact resistance and Composite Material (CMML-3) had the lowest maximum frictional coefficient of friction. 'CM' and 'ML' are initialisms for 'Composite Material' and 'Material of Lubrication' respectively. The number that is attached to the material name is a numeric value that was set by this laboratory.

Ag and Pd electrical contact pairs are separated at constant separating speeds (5, 10 and 20 mm/s) in a DC 42 V/8.4 A resistive circuit. The motion of the breaking arc is observed with a high-speed video camera. For Ag contacts, the motion of the breaking arc becomes stable at a certain critical gap at separating speeds of 10 mm/s and 20 mm/s, and the breaking arc moves extensively at the separating speed of 5 mm/s. For Pd contacts, the breaking arc moves extensively regardless of the separating speed. These results are attributed to the following causes. For Ag contacts, the difference in the motion of arc spots at each separating speed is changed by the difference in the total energy input to the contacts. For Pd contacts, the temperature of the contact surfaces is kept high because of the lower thermal conductivity of Pd than Ag.

Asymmetric Slope Dual Mode Differential Logic (ASDMDL) embodies high-speed dynamic and low-power static operations in a single design. Two-phase dual-rail logic signaling is used in a high-speed operation, where a logical evaluation is preceded by pre-charge, and it asserts one of the rails with an asymmetrically shortened rise transition to express a binary result. On the other hand, single-phase differential logic signaling eliminates pre-charge and leads to a low-power static operation. The operation mode is defined by the logic signaling styles, and no control signal is needed in the logic cell. The design of mixed CMOS and ASDMDL logic circuits can be automated with general logic synthesis and place-and-route techniques, since the physical ASDMDL cell is prepared in such a way to comply with a CMOS standard-cell design flow. A mixed ASDMDL/CMOS micro-processor in a 0.18-µm CMOS technology demonstrated 232 MHz operation, corresponding to 14% speed improvement over a full CMOS implementation. This was achieved by substituting ASDMDL cells for only 4% of the CMOS logic cells in data paths. The low-speed operation of ASDMDL at 100 MHz was nearly equivalent to that of CMOS. However, power consumption was reduced by 3% due to the use of ASDMDL complex logic cells. Area overhead was less than 4%.

This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.

A novel configuration method called Row Multicast Configuration (RoMultiC) is proposed for high speed configuration of coarse grain reconfigurable systems. The same configuration data can be transferred in multicast fashion to configure many Processing Elements (PEs) by using a multicast bit-map provided in row and column directions of PE array. Evaluation results using practical applications show that a model reconfigurable system that incorporates this scheme can reduce configuration clock cycles by up to 73.1% compared with traditional configuration delivery scheme. Amount of required memory to store the configuration data at external memory is also reduced by omitting the duplicated configuration data.

The uni-traveling-carrier photodiode (UTC-PD) is an innovative PD that has a unique operation mode in which only electrons act as the active carriers, resulting in ultrafast response and high electrical output power at the same time. This paper describes the features of the UTC-PD and its excellent performance. In addition, UTC-PD-based optoelectronic devices integrated with various elements, such as passive and active devices, are presented. These devices are promising for various applications, such as millimeter- and submillimeter-wave generation up to the terahertz range and ultrafast optical signal processing at data rates of up to 320 Gbit/s.

Ultrahigh-speed fiber lasers operating at up to 40 GHz offer a clean longitudinal comb and a narrow linewidth. This makes them suitable for applications including optical comb generation, ultrahigh-speed optical pulse transmission including PSK, and as opto-microwave oscillators. In this paper, we describe recent progress on ultrafast fiber lasers and their applications to optical metrology.

In road-vehicle communication systems, the transmission rate between user terminals in the vehicle and the access points degrades due to changing path-loss and time-varying fading. In this paper, we used an inter-vehicle packet relay technique to improve channel quality in road-vehicle communication systems. We evaluated this method using numerical analysis to validate our method.

Diseases of the gastro-intestinal tract are becoming more prevalent. New techniques and devices, such as the wireless capsule endoscope and the telemetry capsule, that are able to measure the various signals of the digestive organs (temperature, pH, and pressure), have been developed for the observation of the digestive organs. In these capsule devices, there are no methods of moving and grasping them. In order to make a swift diagnosis and to give proper medication, it is necessary to control the moving speed of the capsule. This paper presents a wireless system for the control of movements of an electrical stimulus capsule. This includes an electrical stimulus capsule which can be swallowed and an external transmitting control system. A receiver, a receiving antenna (small multi-loop), a transmitter, and a transmitting antenna (monopole) were designed and fabricated taking into consideration the MPE, power consumption, system size, signal-to-noise ratio and the modulation method. The wireless system, which was designed and implemented for the control of movements of the electrical stimulus capsule, was verified by in-vitro experiments which were performed on the small intestines of a pig. As a result, we found that when the small intestines are contracted by electrical stimuli, the capsule can move to the opposite direction, which means that the capsule can go up or down in the small intestines.

We have proposed a diffusion-type flow control mechanism to achieve the extremely time-sensitive flow control required for high-speed networks. In this mechanism, each node in a network manages its local traffic flow only on the basis of the local information directly available to it, by using predetermined rules. In this way, the implementation of decision-making at each node can lead to optimal performance for the whole network. Our previous studies concentrated on the flow control for a single flow. In this paper, we propose a diffusion-type flow control mechanism for multiple flows. The proposed scheme enables a network to quickly recover from a state of congestion and to achieve fairness among flows.

A high-speed drive technique is introduced in which addressing is done by eliminating, instead of accumulating, the wall charges. In the proposed scheme, wall charges are accumulated in all the cells in advance, and then the address discharges take place in selected cells to eliminate the wall charges. Sustain discharges are generated in these cells. In order to realize the proposed address scheme, re-designing of a setup waveforms was necessary. The data pulse of 1.33 µs wide and 84 V was realized in a Ne+10%Xe PDP. A contrast of 3,600:1 was obtained by providing one setup period in a TV field.

In current IP-based networks, the application of window-based end-to-end flow control, including TCP, to ensure reliable flows is an essential factor. However, since such a flow control is provided by the end hosts, end-to-end control cannot be applied to decision-making in a time-scale shorter than the round-trip delay. We have previously proposed a diffusion-type flow control mechanism to realize the extremely time sensitive flow control that is required for high-speed networks. In this mechanism, each network node manages its own traffic only on the basis of the local information directly available to it, by using predetermined rules. The implementation of decision-making at each node can lead to optimal performance for the whole network. Our previous studies showed that the mechanism works well, by itself, in high-speed networks. However, to apply this mechanism to actual networks, it needs to be able to coexist with other existing protocols. In this paper, we investigate the performance of diffusion-type flow control coexisting with TCP. We show that diffusion-type flow control can coexist with TCP and the two can be complementary. Then, we show that a combination of both controls achieves higher network performance than TCP alone in high-speed networks.

A 1-Gb AG-AND flash memory has been fabricated using 0.13-µm CMOS technology, resulting in a cell area of 0.104 µm2 and a chip area of 95.2 mm2. By applying constant-charge-injection programming and source-line-select programming, a fast page programming time of 600 µs is achieved. The four-bank operation attains a fast programming throughput of 10 MB/s in multilevel flash memories. The compact SRAM write buffers reduce the chip area penalty. A rewrite throughput of 8.3 MB/s is achieved by means of the RAM-write operation during the erase mode.

In this paper, a high-speed logic circuitry using bootstrapped and low-temperature polysilicon (LTPS) technologies for TFT-LCD panels is proposed. The new circuitry realizes high-speed operation owing to the application of a logic-swing voltage that is wider than the power-supply voltage using bootstrapped technology. As a result, the new logic circuitry can be operated at an operational frequency around 3-10 times higher than that of the conventional circuitry under the conditions of a 0.5 pF load capacitor at the output of a noninverting buffer and +10 V power-supply voltages. The new circuit is named "BST-TFT logic circuitry."

Combined input and output queuing (CIOQ) switches are being considered as high-performance switch architectures due to their ability to achieve 100% throughput and perfectly emulate output queuing (OQ) switch performance with a small speedup factor S. To realize a speedup factor S, a conventional CIOQ switch requires the switching fabric and memories to operate S times faster than the line rate. In this paper, we propose to use a CIOQ switch with space-division multiplexing expansion and grouped input/output ports (SDMG CIOQ switch for short) to realize speedup while only requiring the switching fabric and memories to operate at the line rate. The cell scheduling problem for the SDMG CIOQ switch is abstracted as a bipartite k-matching problem. Using fluid model techniques, we prove that any maximal size k-matching algorithm on an SDMG CIOQ switch with an expansion factor 2 can achieve 100% throughput assuming input line arrivals satisfy the strong law of large numbers (SLLN) and no input/output line is oversubscribed. We further propose an efficient and starvation-free maximal size k-matching scheduling algorithm, kFRR, for the SDMG CIOQ switch. Simulation results show that kFRR achieves 100% throughput for SDMG CIOQ switches with an expansion factor 2 under two SLLN traffic models, uniform traffic and polarized traffic, confirming our analysis.