Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.

High luminance and high speed response with the cut-off frequency of more than 50 MHz in multilayer polyfluorene-based light-emitting diodes with an interlayer were achieved. We realized multilayer polyfluorene-based light-emitting diodes for frequency response up to 100 MHz.

We demonstrate a single-channel 1.28 Tbit/s-525 km transmission using OTDM of subpicosecond DQPSK signals. In order to cope with transmission impairments due to time-varying higher-order PMD, which is one of the major limiting factors in such a long-haul ultrahigh-speed transmission, we newly developed an ultrafast time-domain optical Fourier transformation technique in a round-trip configuration. By applying this technique to subpicosecond pulses, transmission impairments were greatly reduced, and BER performance below FEC limit was obtained with increased system margin.

Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.

A novel approach for fast traffic classification for the high speed networks is proposed, which bases on the protocol behavior statistical features. The packet size and a new parameter named "Estimated Protocol Processing Time" are collected from the real data flows. Then a set of joint probability distributions is obtained to describe the protocol behaviors and classify the traffic. Comparing the parameters of an unknown flow with the pre-obtained joint distributions, we can judge which application protocol the unknown flow belongs to. Distinct from other methods based on traditional inter-arrival time, we use the "Estimated Protocol Processing Time" to reduce the location dependence and time dependence and obtain better results than traditional traffic classification method. Since there is no need for character string searching and parallel feature for hardware implementation with pipeline-mode data processing, the proposed approach can be easily deployed in the hardware for real-time classification in the high speed networks.

This paper presents a newly developed small-sized shaped beam base station antenna in order to reduce inter-sector interference for next generation high speed wireless data communication systems. The developed antenna realizes polarization diversity as a single small-sized antenna without decreasing the 3 dB main beamwidth compared with the conventional antenna by applying a newly designed beam shaping method. Furthermore, side sub-reflectors are newly installed in the radome to reduce the antenna beam gain in the direction toward the edge region neighboring the other sectors of the horizontal antenna pattern. By adopting this type of reflector, the diameter of the radome can be minimized at 0.65 λ, which is slightly longer than that of the conventional antenna. Both a computer simulation and a field measurement test based on an actual cellular network were conducted for the purpose of clarifying the validity of the shaped beam antenna. In the results, the CINR at the service area by the shaped beam antenna was 1 dB and 3.5 dB better than that of the conventional antenna at the median and 10% of CDF, respectively. The developed antenna will be expected to contribute to the enhancement of the quality of cellular radio systems in the future.

Break arcs are generated between pure silver electrical contacts in a DC high-voltage resistive circuit. The break arc is driven by the external magnetic field of a permanent magnet from horizontal direction of contacts. Electrical contacts are separated at constant opening speed at 75 mm/s. The maximum supply voltage is 300 V. The maximum circuit current when electrical contacts are closed is 20 A. The maximum output power of the supply is limited to 6.0 kW. The gap between the contacts and the magnet is defined as x. The gap is varied from 2.5 mm to 10.0 mm to change the magnetic flux density that affects the break arc. The break arc is observed with a high-speed camera. The effect of the magnetic field on the arc duration was examined. As a result, break arcs are successfully extinguished by the transverse magnetic field when the gap x is 2.5 mm. Then the length of the break arc just before lengthening of the break arc L and the Lorentz force that affects the break arc F are examined. The length L was almost constant for each gap x and independent of the circuit current I and the Lorentz force F. The break arc is driven by the magnetic field when the arc length reached a certain length that was determined by the strength of the magnetic flux density.

In order to clarify the physics of contact life time, the relationship between heat capacity of holder and shape of bridge (length and diameter) is discussed in this paper. The AgPd60 alloy is chosen as electrode material. Two holders with different heat capacity are comprised of copper plate and cylinder. The shape of the bridge at the low speed breaking contact is observed by using the high speed digital camera. It was demonstrated that the shape of the bridge is changed by the response and distribution of the temperature.

A monolithic modulator driver IC based on InP HBTs with a new circuit topology -- called a functional distributed circuit (FDC) -- for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2:1 multiplexing function produces 2.6-Vp-p (differential output: 5.2 Vp-p) and 2.4- Vp-p (differential output: 4.8 Vp-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80 Gb/s and 90 Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO3 Mach-Zehnder modulator up to 90 Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.

This paper presents a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower supply voltage. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects. Also, a new data-dependent adaptive time-domain pre-emphasis technique is proposed to compensate for the data-dependent jitter.

Noise coupling on the power distribution networks (PDN) or between PDN and signal traces is becoming one of the main challenges in designing above GHz high-speed digital circuits. Developing an efficient and accurate modeling method is essential to understand the noise coupling mechanism and then solve the problem afterwards. In addition, development of new noise mitigation technology is also important for future high-speed circuit systems. In this invited paper, a novel modeling methodology that is based on the physics-based equivalent circuit model will be introduced, and an example of multiple layer PCB circuits will be modeled and validated with good accuracy. Based on the periodic structure concept, several new electromagnetic bandgap structures (EBG), such as coplanar EBG, photonic crystal power layer (PCPL), and ground surface perturbation lattice (GSPL), will be introduced for the mitigation of power/ground noise. The trade/offs of all these structures will be discussed.

We investigated the effect of a high-speed power line communication (PLC) signal induced into a very high-speed digital subscriber line (VDSL) system by conductive coupling based on a network model. Four electronic devices with AC mains and telecommunication ports were modeled using a 4-port network, and the parameters of the network were obtained from measuring impedance and transmission loss. We evaluated the decoupling factor from the mains port to the telecommunication port of a VDSL modem using these parameters for the four electric and electronic devices. The results indicate that the mean value of the decoupling factor for the differential and common mode signals were more than 88 and 62 dB, respectively, in the frequency range of a PLC system. Taking the following parameters into consideration; decoupling factor Ld, the average transmission signal powers of VDSL and PLC, desired and undesired (DU) ratio, and transmission loss of a typical 300-m-long indoor telecommunication line, the VDSL system cannot be disturbed by the PLC signal induced into the VDSL modem from the AC mains port in normal installation.

Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.

This paper presents a CMOS signal detection circuit for 2.5 Gb/s serial data communication system over FR-4 backplane. This overcomes characteristics deviation of full-wave rectifier-based simple power detection circuits due to data pattern and temperature by using an edge detector and a sample-hold circuit.

With the emergence of bandwidth-greedy application services, high-speed transport protocols are expected to effectively and aggressively use large amounts of bandwidth in current broadband and multimedia networks. However, when high-speed transport protocols compete with other standard TCP flows, they can occupy most of the available bandwidth leading to disruption of service. To deploy high-speed transport protocols on the Internet, such unfair situations must be improved. In this paper, therefore, we propose a method to improve fairness, called Kyushu-TCP (KTCP), which introduces a non-aggressive period in the congestion avoidance phase to give other standard TCP flows more chances of increasing their transmission rates. This method improves fairness in terms of the throughput by estimating the stably available bandwidth-delay product and adjusting its transmission rate based on this estimation. We show the effectiveness of the proposed method through simulations.

The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

Substrate noise analysis has become increasingly important in recent LSI design. This is because substrate noise, which affects PLLs, causes jitter that results in timing error. Conventional analysis techniques of substrate noise are, however, impractical for large-scale designs that have hundreds of millions of transistors because the computational complexity is too huge. To solve this problem, we have developed a fast substrate noise analysis technique for large-scale designs, in which a chip is divided into multiple domains and the circuits of each domain are reduced into a macro model. Using this technique, we have designed a processor chip for use in the supercomputer (die size: 20 mm 21 mm, frequency: 3.2 GHz, transistor count: 350M). Computation time with this design is five times faster than that with a 1/3000 scale design using a conventional technique, while resulting discrepancy with measured period jitter is less than 15%.

In this paper, new structure of Voltage-Mode MAX-MIN circuit are presented for nonlinear systems, fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, high precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors for each extra input. The proposed circuit which is simulated by HSPICE in 0.35 µm CMOS process shows the total power consumption of 85 µW in 5 MHz operating frequency from a single 3.3-V supply. Also, the total area of the proposed circuit is about 420 µm2 for two input voltages, and would be negligibly increased for each extra input.

Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is promising to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using adders in subthreshold operation in a 90 nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.

The paper introduces both high-speed transmission and quality of system to offer the Internet services on a HFC (Hybrid Fiber Coaxial) network. This utilizes modulating the phase and the amplitude to the signal of the IPMS (Internet Protocol Multicasting Service). An IP-cable transmitter, IP-cable modem, and IP-cable management servers that support 30-Mbps IPMS on the HFC were developed. The system provides a 21 Mbps HDTV transporting stream on a cable TV network. It can sustain a clear screen for a long time.