The motion of arc spots of breaking arc is investigated for Ag electrical contacts in DC 42 V/10 A resistive circuit using a high-speed camera. Also, the eroded contact surfaces are observed with a microscope after each breaking operation. As results, some kinds of different films and eroded regions are distinguished. Diameters of these regions are corresponding to the widths of the cathode and anode spot regions that are obtained by using the high-speed camera. It is found that the films and eroded regions on the electrical contacts are generated at different stages of the breaking arc.

In each contact material (Ag, Cu, Ni, and Fe), the breaking arcs occurring between an electrical contact pair in a resistive circuit of DC42 V/10.5 A were observed with a high-speed camera (1000 frames/s). Arc voltage and arc current were also measured simultaneously. By analyzing cathode and anode bright spots in the photographs, the positions of cathode and anode bright spots on contact surfaces were plotted on the graph. As a result, cathode and anode bright spots were found to express the characteristic motion in each material. Moreover, by comparing those results with the photograph of contact surface after all operations.

Continuous and explosive growth of the Internet has shown that current TCP mechanisms can obstruct efficient use of high-speed, long-delay networks. To address this problem we propose an enhanced transport-layer protocol called gHSTCP, based on HighSpeed TCP proposed by Sally Floyd. It uses two modes in the congestion avoidance phase based on the changing trend of RTT. Simulation results show gHSTCP can significantly improve performance in mixed environments, in terms of throughput and fairness against the traditional TCP Reno flows. However, the performance improvement is limited due to the nature of TailDrop router, and the RED/ARED routers can not alleviate the problem completely. Therefore, we present a modified version of Adaptive RED, called gARED, directed at the problem of simultaneous packet drops by multiple flows in high speed networks. gARED can eliminate weaknesses found in Adaptive RED by monitoring the trend in variation of the average queue length of the router buffer. Our approach, combining gARED and gHSTCP, is quite effective and fair to competing traffic than Adaptive RED with HighSpeed TCP.

In order to control the moving speed of an endoscopic capsule in the human intestine, electrical stimulation method is proposed in this paper. The miniaturized endoscopic capsule with the function of various electrical stimulations has been designed and implemented. An in-vivo animal experiment has been performed to show the ability of controlling the movement speed of the endoscopic capsule according to the level of electrical stimulation. In-vivo experiments were performed by inserting the implemented capsule into a pig's intestinal tract. From the experimental results, the activation of peristaltic movement and the relationship between the moving speed of capsule and the stimulation amplitude could be found. It is shown that the moving speed of capsule in the intestine can be controlled by adjustment of the stimulation level applied in the capsule electrodes. The results of the in-vivo experiment verify that the degree of contraction in the intestinal tract is closely related with the level of stimulating electrical voltage, suggesting that the moving speed of capsule in the human gastrointestinal tract can be controlled by externally adjusting the amplitude of stimulating pulse signal.

This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects and time-variant clock skew between ICs should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches GHz range. A robust FIFO built in the D/A converter can absorb input data timing variance due to the capacitive coupling and the clock timing skew, the worst-case margin of which is 1.5TCLK. Distributed RLC transmission line models for on-chip interconnects produce accurate simulation results at 1 GHz clock frequency over lumped models. For optimized D/A converter design, behavioral modeling methodology is also presented in this paper. Measurement results verify the accuracy of the on-chip interconnect and behavioral models.

This paper describes a speed-oriented ultralow-voltage and low-power SOI circuit technique based on a differential enhancement- and depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-Vth CMOS circuit block for noncritical paths, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to achieve low-power and ultrahigh-speed operation of over 1 GHz at a supply voltage of less than 0.5 V. As two applications of the differential ED-CMOS/SOI circuit, a multi-stage frequency divider that uses the ED-MOS circuit in a first-stage frequency divider and a pipelined adder with a CMOS pipeline register are described in detail. To verify the effectiveness of the ED-CMOS/SOI circuit scheme, we fabricated a 1/8 frequency divider and a 32-bit binary look-ahead carry (BLC) adder using the 0.25-µm MTCMOS/SOI process. The frequency divider operates down to 0.3 V with a maximum operating frequency of 3.6 GHz while suppressing power dissipation to 0.3 mW. The 32-bit adder operates at a frequency of 1 GHz at 0.5 V.

This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.

Based on the similarity in current-voltage characteristics of resonant-tunneling diodes (RTDs) and tunneling-type superconductive Josephson junctions, novel current-mode logic circuits consisting of four RTDs have been proposed. NAND and NOR functions, as well as AND and OR, can be obtained in a simple circuit configuration. SPICE simulation showed that the present circuits can operate at a clock frequency as high as 200 GHz.

We have proposed diffusion-type flow control as a solution for the extremely time-sensitive flow control required for high-speed networks. In our method of flow control, we design in advance simple and appropriate rules for action at the nodes, and these automatically result in stable and efficient network-wide performance through local interactions between nodes. Specifically, we design the rules for the flow control action of each node that simulates the local interaction of a diffusion phenomenon, in order that the packet density is diffused throughout the network as soon as possible. However, in order to make a comparison with other flow control methods under the same conditions, the evaluations in our previous studies used a closed network model, in which the number of packets was unchanged. This paper investigates the performance of our flow control method for an end-to-end flow, in order to show that it is still effective in more realistic networks. We identify the key issues associated with our flow control method when applied to an open network model, and demonstrate a two-step solution. First, we consider the rule for flow control action at the boundary node, which is the ingress node in the network, and propose a rule to achieve smooth diffusion of the packet density. Secondly, we introduce a shaping mechanism, which keeps the number of packets in the network at an appropriate level.

This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.

In this letter, we propose a low-complexity estimation method of cyclic-prefix (CP) length for a discrete multitone (DMT) very high-speed digital subscriber line (VDSL) system. Using the sign bits of the received DMT VDSL signals, the proposed method provides a good estimate of CP length, which is suitable for various channel characteristics. This simple estimation method is consistent with the initialization procedure of T1E1.4 multi-carrier modulation (MCM)-based VDSL Standard. Finally, simulation results with VDSL test loops are presented.

This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high bandwidth of 400 MHz operation with CL=2.5.

It is reported that TCP does not perform well in high-speed wide area networks. Because MulTCP behaves like the aggregate of N TCP flows, MulTCP can be used to achieve throughputs of 1 Gbps or more. However, no performance evaluation of MulTCP in high-speed wide area networks has been published. Computer simulations are used to evaluate the performance of MulTCP. The results clarify that synchronized packet losses greatly impact the performance of MulTCP.

This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.

This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes a high-speed layout synthesis for CMOS logic cells and guarantees to generate the minimum-width cells with routability under our layout styles. It considers complementary P-/N-MOSFETs individually during transistor placement, and can generate smaller width layout compared with pairing the complementary P-/N-MOSFETs case. To demonstrate the effectiveness of our SAT-based cell synthesis, we present experimental results which compare it with the 0-1 ILP-based transistor placement method and a commercial cell generation tool. The experimental results show that our SAT-based method can generate minimum-width placements in much shorter run time than the 0-1 ILP-based transistor placement method, and can generate the cell layouts of 32 static dual CMOS logic circuits in 54% run time compared with the commercial tool. Area increase of our method without compaction is only 3% compared with the commercial tool with compaction.

The most important function of a router is to perform IP lookup that determines the output ports of incoming IP packets by their destination addresses. Hence, IP lookup is one of the main issues in implementing high-speed routers. The IP lookup algorithm implemented in IQ2200 Chipset with two-level table architecture can efficiently use memory. However, it wastes processor resource for full re-construction of the forwarding tables whenever every route insertion/deletion is requested. In order to improve the utilization of processor resource, we propose an IP lookup algorithm with three-level table architecture for high-speed routers. We evaluate the performance of the proposed algorithm in terms of the memory size required for storing lookup information and the number of memory access in constructing forwarding tables. Being compared with the IQ2200 scheme, the proposed scheme can reduce the number of memory access up to 99% even though it needs about 16% more memory.

This paper reviews process, device and circuit technologies of high-density flash memories, whose market has grown explosively as bridge media. In this memory, programming throughput as well as low bit costs is critical issue. To meet the requirements, we have developed multi-level AG (Assist Gate)-AND type flash memory with small effective cell size and 10 MB/s programming throughput. We clarify three challenges to the multilevel flash memory in terms of operation method, high reliability for data retention, and high-speed multilevel programming. Future trends of high-density flash memories are also discussed.

A Power on Reset signal generation circuit referencing threshold voltage without standby current consumption has been proposed. The POR signal is generated when supply voltage is larger than the sum of threshold voltages of N- and P-MOSFET.

The purpose of this study is to examine the impact of the opening speed on a breaking arc. The opening speeds are 10, 20 and 30 mm/s. The breaking arc is generated in a D.C. 42 V/10.5 A circuit, and the arc voltage, the arc current, the gap length and the arc spectrum intensity are measured. Arc temperature is calculated by using a Boltzmann plot. Even if the opening speed is changed, the arc temperature starts from a high temperature, and falls gradually to 4650-4750 K with time. Namely, the opening speed has no influence on the arc temperature.

Breaking arcs occurring between Ag or Cu electrical contact pairs in DC 56 V/7 A resistive circuit are observed with a high-speed camera (1000 frames/s). As a result, the increase of brightness of the arc-emitted light synchronizes with the increase of arc current in the latter half of arc duration. For the case of Ag contacts, the brightness increases in entire region of the breaking arc with sudden increase of the arc current. On the other hand, the increase of the intensity for Cu contacts occurs in not only entire discharge region but also anode spot region significantly.