This paper investigates the effect of fast cell selection (FCS) associated with fast packet scheduling methods and hybrid automatic repeat request (HARQ) with Chase combining, in which the optimum cell (or sector) transmitting a slot-assigned downlink shared channel (DSCH) is selected based on the received signal-to-interference power ratio (SIR), in high-speed downlink packet access (HSDPA). The Round robin (RR), Proportional fairness (PF) and Maximum carrier-to-interference power ratio (CIR) schedulers are used as the scheduling algorithm. The simulation results elucidate that although almost no additional diversity gain through FCS is obtained for the PF and Maximum CIR schedulers, the improvement in throughput by FCS coupled with the RR scheduler is achieved. Furthermore, we elucidate that the effect of FCS is small when only inter-sector FCS is performed; however, inter-cell FCS is effective in improving the radio link throughput for the access users with a lower received SIR near the cell edge. The radio link throughput at the cumulative distribution of 20% of soft handover users when both inter-sector and inter-cell FCS are performed is increased by approximately 20% and 60% for PF and RR schedulers, respectively, compared to that without FCS, i.e. with hard handover. We also show that when a traffic model such as the modified ETSI WWW browsing model is taken into account, the effect of FCS associated with the decreasing effect of fast packet scheduling is greater than that assuming continuous packet transmission. The user throughput at the cumulative distribution of 20% employing both inter-sector and inter-cell FCS is increased by approximately 60% compared to that without FCS.

We propose a buffer management mechanism, called V-WFQ (Virtual Weighted Fair Queueing), for achieving an approximately fair allocation of bandwidth with a small amount of hardware in a high-speed network. The basic process for the allocation of bandwidth uses selective packet dropping that compares the measured input rate of the flow with an estimated fair share of bandwidth. Although V-WFQ is a hardware-efficient FIFO-based algorithm, it achieves almost ideal fairness in bandwidth allocation. V-WFQ can be implemented in the high-speed core routers of today's IP backbone networks to provide various high-quality services. We have investigated V-WFQ's performance in terms of fairness and link utilization through extensive simulation. The results of simulation show that V-WFQ achieves a good balance between fairness and link utilization under various simulation conditions.

This paper presents a comparison of the throughput performance employing hybrid automatic repeat request (HARQ) with packet combining, such as Type-I with packet combining (simply Chase combining hereafter) and Type-II (Incremental redundancy hereafter), using turbo coding in a multipath fading channel in high speed downlink packet access (HSDPA). We apply a multipath interference canceller (MPIC) to remove the influence of severe multipath interference. Link level simulation results show that the maximum throughput using Incremental redundancy with 64QAM is improved by approximately 5-8% compared to that using Chase combining, and that the required average received signal energy of 12 code channels per chip-to-background noise spectrum density (Ec/N0) at the throughput of 4 Mbps with Incremental redundancy is decreased by approximately 1.0 dB rather than that with Chase combining when the vehicular speed is higher than approximately 30 km/h. Furthermore, we elucidate based on the system level simulation that although no improvement is obtained in a slow mobility environment such as the average vehicular speed of 3 km/h, the achieved throughput of Incremental redundancy is increased by approximately 5-6% and 13% for the average vehicular speed of 30 km/h and 120 km/h, respectively, compared to that with Chase combining.

The problem of finding a path with two additive constraints, in particular finding a path that satisfies both the cost and the delay constraints, is called multi-constrained path (MCP) problem in the literature. In this paper, we explore the MCP problem based on the idea of single mixed weight --a mixed weight for each link is first obtained by combining its delay and cost, and then Dijkstra's algorithm is used to find the corresponding shortest path. Given two infeasible paths, it can be theoretically proved that a better path can possibly be found if we choose an appropriate parameter to construct the mixed weight. An approximate algorithm is thus proposed to solve the MCP problem. Theoretical analysis demonstrates that this algorithm can make a correct judgment whether there is a feasible path or not with a very high probability even in the strict case where the delay bound is between the delays of the least delay path and the least cost path, while the cost bound is between the costs of the two paths. On the other hand, the time complexity of this algorithm is very small since it only needs to execute Dijkstra's algorithm a limited number of times. The excellent performance of the proposed algorithm is verified by a large number of experiments on networks of different sizes.

In this paper, we present the division algorithm (DA) for the computation of b=c/a over GF(2m) in two aspects. First, we derive a new formulation for the discrete-time Wiener-Hopf equation (DTWHE) Ab = c in GF(2) over any basis. Symmetry of the matrix A is observed on some special bases and a three-step procedure is developed to solve the symmetric DTWHE. Secondly, we extend a variant of Stein's binary algorithm and propose a novel iterative division algorithm EB*. Owing to its structural simplicity, this algorithm can be mapped onto a systolic array with high speed and low area complexity.

Phase-inversion between neighboring pulses appearing in carrier-suppressed return-to-zero pulses is effective in reducing the signal distortion due to chromatic dispersion and nonlinear effects. A generation method of the anti-phase pulses at 40 GHz is demonstrated by using semiconductor mode-locked lasers integrated with chirped gratings. Operation principle and pulse characteristics are described. Suppression of pulse distortion due to fiber dispersion is confirmed for generated anti-phase pulses. Repeaterless 150-km dispersion-shifted-fiber L-band transmission at 42.7 Gbit/s is demonstrated by using the pulse source.

Power-line communication (PLC) systems have been assumed as the systems of low speed and low reliability. The low qualities of the systems, however, are not inherent of PLC but the result of inadequate design strategy of the systems. The systems with proper considerations of the characteristics of power-line as a communication medium achieve reliable high-speed data transmission in power-lines. In fact, the activities on the standardization of high-speed PLC systems have recently started in many countries, and variety of high-speed PLC systems are being to be purchased off-the-shelf. Following this trend of PLC, this manuscript first describes the features of power-line for communications and then explains technical issues on the design of PLC systems of the next generations as the infrastructure of information-communication technology age.

Network bandwidth has rapidly increased, and high-speed networks have come into wide use, but overheads in legacy network protocols prevent the bandwidth of networks from being fully utilized. Even UDP, which is far lighter than TCP, has been a bottleneck on high-speed networks due to its overhead. This overhead mainly occurs from per-byte overhead such as data copy and checksum. Previous works have tried to minimize the per-byte overhead but are not easily applicable because of their constraints. The goal of this paper is to investigate how to fully utilize the bandwidth of high-speed networks. We focus on eliminating data copy because other major per-byte overhead, such as checksum, can be minimized through hardware. This paper introduces a new concept called Asynchronous UDP and shows that it eliminates data copy completely. We implement Asynchronous UDP on Linux with ATM and present the experiment results. The experiments show that Asynchronous UDP is much faster than the existing highly optimized UDP by 133% over ATM. In addition to the performance improvement, additional advantages of Asynchronous UDP include: (1) It does not have constraints that previous attempts had, such as copy-on-write and page-alignment; (2) It uses much less CPU cycles (up to 1/3) so that the resources are available for more connections and/or other useful computations; (3) It gives more flexibility and parallelism to applications because applications do not have to wait for the completion of network I/O but can decide when to check the completion.

A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.

This paper describes the recent progress in the device performance of the uni-traveling-carrier photodiode (UTC-PD). The UTC-PD utilizes only electrons as the active carriers and this unique feature is the key to achieving excellent high-speed and high-output characteristics simultaneously. The achieved performance includes a record 3-dB bandwidth (f3dB) of 310 GHz, a high output current over 180 mA with an f3dB of 65 GHz, a high linearity of up to 80 mA, and a zero-bias operation with an f3dB of 230 GHz and an output peak current of 6.8 mA.

InP-based high electron mobility transistors (HEMTs) with gate lengths reduced to 30 nm were fabricated and characterized, and the effect of the gate recess on the high-frequency characteristics was studied. The cutoff frequency, which is regarded as a function of the gate length and the average carrier velocity in a first-order approximation, depends on the size of the gate recess when the gate length becomes short. The size of the gate recess is optimized by taking the feed-back capacitance and the parasitic resistance into account. For HEMTs having the gate recess with an InP surface, an appropriate widening of the gate recess gives a record cutoff frequency of 368 GHz for the 30-nm-gate HEMTs with a lattice-matched channel.

In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.

Sector antennas provide many advantages such as when combined with a narrow beam antenna, they become particularly effective in achieving high-speed wireless communication systems and they aid in simplifying the structure. These antennas have a drawback in that as the number of sectors increases, the antenna size rapidly increases. Therefore, downsizing the sector antenna has become a major research topic. A promising candidate is utilizing a phased-array type antenna; however, this antenna requires a phase-shifter circuit for beam scanning and generally the feeding circuit for this type of antenna is very complicated. To address these issues, we propose a self-selecting feeding circuit that is controlled by the same control circuit and is operated similarly to the conventional single port n-th throw (SPNT) switch. We fabricated a small cylindrical 12-sector antenna at 19 GHz employing the proposed feeding circuit for verification purposes. Furthermore, this paper clarifies the design method of this feeding circuit where the antenna diameter is 71 mm, and the results clearly show that the gain is more than 12 dBi.

This paper elucidates the most appropriate hybrid automatic-repeat-request (ARQ) scheme, i.e., which can achieve the highest throughput, for high-speed packet transmission in the W-CDMA forward link by comparing the throughput performance of three types of hybrid ARQ schemes: type-I hybrid ARQ with packet combining (PC), type-II hybrid ARQ, and basic type-I hybrid ARQ as a reference. Moreover, from the viewpoint of maximum throughput, the respective optimum roles of ARQ and channel coding in hybrid ARQ are also clarified, such as the optimum coding rate and the packet length related to the interleaving effect. The simulation results reveal that the type-II scheme exhibits the best throughput performance, and the required received signal energy per chip-to-background noise spectral density ratio (Ec/N0) at the throughput efficiency of 0.2/0.4/0.6 is improved by 0.7/0.3/0.1 dB and 3.9/1.8/0.5 dB, respectively, compared to the type-I scheme with and without PC in a 2-path Rayleigh fading channel with the average equal power at the maximum Doppler frequency of 5 Hz and the packet length of 4 slots (= 0.667 4 = 2.667 msec). However, the improvement of the type-II scheme compared to the type-I scheme with PC is small or the achievable throughput is almost identical in the high-received Ec/N0 region. On the other hand, the type-I scheme with PC is much less complex and thus preferable, while maintaining almost the same throughput performance or allowing very minor degradation compared to that with type-II. The results also elucidate that, while the optimum coding rate depends on the required throughput in the basic type-I and type-I with PC schemes, it is around between 3/4 and 8/9 in type-II, resulting in a higher throughput efficiency. In addition, for high-speed packet transmission employing a hybrid ARQ scheme, a shorter retransmission unit size is preferable such as 1 slot, and the fast transmit power control is effective only under conditions such as a low maximum Doppler frequency and a high transmit Ec/N0 region.

EMI coupling paths in an electronic controller are investigated experimentally. Common-mode current measurements on the attached cable are used for diagnosing changes made to the EMI coupling path. Experiments that include shielding various portions of the PCB, and re-routing high-speed traces are conducted to characterize the coupling path. A means of identifying and characterizing EMI coupling paths in functioning hardware, and relating them to design features, is demonstrated.

A small data-line-swing read/write scheme is described for half-Vcc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-Vcc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.

The hardware implementation of a proposed high dimensional discrete torus knot code was successfully realized on an ASIC chip. The code has been worked on for more than a decade since then at Aichi Prefectural University and Nagoya Institutes of Technology, both in Nagoya, Japan. The hardware operation showed the ability to correct the errors about five to ten times the burst length, compared to the conventional codes, as expected from the code configuration and theory. The result in random error correction was also excellent, especially at a severely degraded error rate range of one hundredth to one tenth, and also for high grade characteristic exceeding 10-6. The operation was quite stable at the worst bit error rate and realized a high speed up to 50 Mbps, since the coder-decoder configuration consisted merely of an assemblage of parity check code and hardware circuitry with no critical loop path. The hardware architecture has a unique configuration and is suitable for large scale ASIC design. The developed code can be utilized for wider applications such as mobile computing and qualified digital communications, since the code will be expected to work well in both degraded and high grade channel situations.

We propose a dynamic assignment method of radio channels using their qualities and data packet sizes. In this method, a high quality channel is assigned for long packets and a low quality channel is assigned for short packets. Assuming a packet transfer method based on PHS (Personal Handy System) procedure, the transfer speed and delay characteristics are investigated by computer simulation and compared with conventional method (i.e. random assignment). Both the transfer speed characteristics and delay performance are improved under light traffic load.

A novel body potential-controlling technique for floating SOI CMOS circuits is proposed and verified in this study. High-speed operation is realized with a small chip size by using body-floating SOI transistors. The use of this technique allows the threshold voltage of the body-floating transistors to be varied transitionally. Therefore, the standby current of SOI CMOS logic is reduced to less than 1/50th of that required by the non-controlled operation of the body potential, and the logic operates at a high speed during the active period. There is no speed penalty for the recovery operation from the standby mode. This technique supports sub-1 V operation, which will be required by future battery-operated devices with wide-range covering.

2.4-GHz-band mid-speed (1- to 2-Mbit/sec) wireless LAN systems are being widely used in offices and factories. Electromagnetic interference can occur between these systems because they use the same frequency range. In this paper, we investigate the characteristics of the interference between wireless LAN systems that use direct-sequence (DS) systems and frequency-hopping (FH) systems. The interference characteristics were measured for three DS systems and one FH system that meet the IEEE 802.11 and RCR standards and that use different modulation methods. Our results indicate that throughput depends on the system and the modulation method. We have also developed a model that can be used to calculate the interference characteristics between DS and FH systems by considering the bandwidth of their transmission signals, the dwell time of the FH system, and the time that the DS system needs to transmit a data frame. We used this model to calculate the bit error rate (BER) characteristics of the systems used in our experiment, and the results indicate that BER characteristics depend on the modulation method. The throughput characteristics of the systems used in our experiment were also calculated, and agreed with the experiment results within +/- 5 dB. The throughput characteristics of wireless LAN systems based on IEEE 802.11 were also calculated when the signal level was higher than the receiver noise level. The results show that FH systems require a D/U ratio about 7 or 8 dB higher than the ratio required in DS systems because the parameters in the standard differ between FH and DS systems.