The architecture design and test results of simulation facility named millimeter-wave Test Bed has been described. Contrast with a millimeter-wave sounder, the Test Bed proposed in this paper can characterize radio channels, received signals, target reflections and radio link performance at the millimeter-wave band of 60 GHz. For fixible simulation and analysis of the performances of newly designed millimeter-wave systems, major digital signal processing parts like a sophisticate waveform generator and an analyzer, a modulator, a demodulator, an encoder, a decoder, an equalizer in the Test Bed are implemented by a software using SPW. This software based Test Bed can be used as a "deign tool" for the simulation of the millimeter-wave communication systems very flexibly without hardware modification in different specifications. The Test Bed consists of a millimeter-wave transmitter, a receiver of 60 GHz, 1.95 GHz up/down converter as IF module and a digital signal processing module. The I/Q vector modulator and demodulator with a video bandwidth of 37.5 MHz in the Test Bed can simulate or test the application of high data rate communication systems of short distance.

In this paper, we present a simple codeword length generation algorithm and its hardware implementation. The proposed technique is based on the dividing the Huffman table as two parts; with leading 0'bits and following bits. The method is shown to be efficient in the memory requirement and searching speed since only logic gates are needed in the implementation and searching can be process parallel without looking up the memory table. The total equivalent gates for the implementation are about only 100 gates and critical path delay is 10 ns. The results of experiments show that the proposed algorithm has a very high speed and a good performance. The designed blocks are synthesized by Compass synthesis with 0.5 µm CMOS, 3.3V, technology.

It is confirmed by simulation that SOI-DRAMs can be operated at high speed by using the floating body structures. Several floating body effects are analyzed. It is described that the dynamic retention characteristics are not dominated by capacitive coupling and hole redistribution. And it is described that those characteristics are determined by the leakage current in the small pn-junction region of the floating body. Reducing pn junction leakage current is important for realizing a long retention time. If the pn junction leakage is suppressed to 10-18 A/µm, a dynamic retention time of 520 sec at a VBSG of 0.5 V can be achieved at 27. On those conditions, the refresh current of SOI-DRAMs is reduced by 54% compared with bulk-Si DRAMs.

This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.

A novel method for the radiated immunity test is proposed. The method is to generate controlled electromagnetic fields applying in arbitrary directions to an under test. The fields rotate at a low speed controlled electrically so that the immunity characteristics may be known in more detail. The primal characteristics of the fields generated by a trial benchtop setup are investigated.

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.

A high-speed static logic circuit, the 1:8 demultiplexer (DEMUX), fabricated using single-gate CMOS technology (single-gate means the structure consisting of n+ poly-Si gate for both NMOS and PMOS transistors) has been demonstrated. To suppress short-channel effects in PMOS transistors, we only used the low-energy ion implantation (I/I) of BF2 at 10 keV for counterdoping of the channel and that at 5 keV for source/drain (S/D) extension. To control the threshold voltage Vth of PMOS transistors precisely, the channel dopants were implanted after the growth of the gate oxide because of the suppression of the transient-enhanced diffusion (TED) of boron, and the suppression of boron out-diffusion. A tree-type 1:8 DEMUX circuit composed of 0. 134 µm gate CMOS transistors operates at a high speed of 3.1 GHz and consumes a low power of 35.5 mW/GHz at VDD = 2.0 V. In this single-gate CMOS circuit, down to this small gate length, the maximum operating frequency of the DEMUX circuit increases proportionally with an increase of the inverse of the gate length without an increase of power consumption per GHz. At a practical 2.48832 Gb/s operation, the power consumption was 88 mW, and the phase margin between the input clock signal and the input data signal was 260 ps. It is suggested that a circuit composed of a single-gate CMOS transistor with 0.15 µm gate generation can be applicable to high speed ICs.

The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.

The distributions of a spectral intensity of the breaking arc between silver contacts in DC 45-66 V/2.5-5.0 A circuits have been measured using a high-speed color video. As a result, a cathode brightening spot, which has a high spectral intensity, exists near the cathode surface. The cathode brightening spot expands with the increase of the contact gap, but its length expands until about 18µm. When the contact gap spreads over about 180 µm, a dark positive column appears and grows between the cathode brightening spot and the anode surface. The higher the interrupted current is, the larger the diameter of the cathode brightening spot will be. The maximum diameter of cathode brightening spot is 500 µm under these experiments.

High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.

This paper proposes a novel ultra high-speed file server based on a personal computer (PC) to provide the instantaneous delivery of huge files, like movie files, graphic images and computer programs, over high-speed networks. In order to improve the sustained sequential read speed from arrays of hard drives to host memory in the server, two key techniques are proposed: "multi-stage striping (MSS)" and the "sequential file system (SFS)." An experimental file server based on a general-purpose PC is constructed and its performance is measured. The results show that the server offers ultra high read speeds, up to 105Mbytes/s, with just 8 hard drives.

We have designed rapid single-flux-quantum (RSFQ) adder circuits using two different architectures: one is the conventional architecture employing globally synchronous clocking and the other is the data-driven self-timed (DDST) architecture. It has been pointed out that the timing margin of the RSFQ logic is very sensitive to the circuit parameter variations which are induced by the fabrication process and the device parameter uncertainty. Considering the physical timing in the circuits, we have shown that the DDST architecture is advantageous for realizing RSFQ circuits operating at very high frequencies. We have also calculated the theoretical circuit yield of the DDST adders and shown that a four-bit system operating at 10 GHz is feasible with sufficient operating margin, considering the present 1 kA/cm2 Nb Josephson technology.

Computational expensiveness of the training techniques, due to the extensiveness of the data set, is among the most important factors in machine learning and neural networks. Oversized data set may cause rank-deficiencies of Jacobean matrix which plays essential role in training techniques. Then the training becomes not only computationally expensive but also ineffective. In [1] the authors introduced the theoretical grounds for dynamic sample selection having a potential of eliminating rank-deficiencies. This study addresses the implementation issues of the dynamic sample selection based on the theoretical material presented in [1]. The authors propose a sample selection algorithm implementable into an arbitrary optimization technique. An ability of the algorithm to select a proper set of samples at each iteration of the training has been observed to be very beneficial as indicated by several experiments. Recently proposed approaches to sample selection work reasonably well if pattern-weight ratio is close to 1. Small improvements can be detected also at the values of the pattern-weight ratio equal to 2 or 3. The dynamic sample selection approach, presented in this article, can increase the convergence speed of first order optimization techniques, used for training MLP networks, even at the value of the pattern-weight ratio (E-FP) as high as 15 and possibly even more.

Conventional approaches to neural network training do not consider possibility of selecting training samples dynamically during the learning phase. Neural network is simply presented with the complete training set at each iteration of the learning. The learning can then become very costly for large data sets. Huge redundancy of data samples may lead to the ill-conditioned training problem. Ill-conditioning during the training causes rank-deficiencies of error and Jacobean matrices, which results in slower convergence speed, or in the worst case, the failure of the algorithm to progress. Rank-deficiencies of essential matrices can be avoided by an appropriate selection of training exemplars at each iteration of training. This article presents underlying theoretical grounds for dynamic sample selection (DSS), that is mechanism enabling to select a subset of training set at each iteration. Theoretical material is first presented for general objective functions, and then for the objective functions satisfying the Lipschitz continuity condition. Furthermore, implementation specifics of DSS to first order line search techniques are theoretically described.

We have developed a multiple quantum well (MQW) electroabsorption (EA) modulator for wavelength-division multiplexing (WDM) switching systems. The fabricated MQW EA gate has low polarization and wavelength-dependent loss and high extinction ratio within the wavelength range of 1545 to 1560 nm. And by using this gate ultra-high-speed switching is achieved for WDM signals. Moreover, we optimize the EA gate for the full gain-band of an erbium-doped fiber amplifier (EDFA)(1535 to 1560 nm). This EA gate provides low polarization-dependent loss, higher extinction ratio, and high saturation input power in the wider wavelength range. These MQW EA gates will play an important role in future WDM switching systems.

It becomes essential in practice to improve a processing rate and to divide an image into small segments adjusting a limited memory, because image filing systems handle large images up to A1 size. This paper proposes a new method of an automatic skew normalization, comprising a high-speed skew detection and a distortion-free dividing rotation. We have evaluated the proposed method from the viewpoints of the processing rate and the accuracy for typed documents. As results, the processing rate is 2. 9 times faster than that of a conventional method. A practical processing rate for A1 size documents can be achieved under the condition that the accuracy of a normalized angle is controlled within 0. 3 degrees. Especially, the rotation with dividing can have no error angle, even when the A1 size documents is divided into 200 segments, whereas the conventional method cause the error angle of 1. 68 degrees.

MTDMA (Multimedia, Multimode TDMA) system has been developed for the 3rd generation mobile communications. An adaptive modulation technique is employed, which select 16 QAM or QPSK modulations fit for the O (Indoor Office)/P (Outdoor to Indoor and Pedestrian) communication environments. The maximum user rate of 4 Mbps is realized. Basic specification is described for O, P and V environments.

The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

The location of stations on the buses can not be ignored in the analysis of the DQDB protocol, especially when traffic load is heavy. In this paper, we propose a new method to model the DQDB (Distributed Queue Dual Bus) protocol by assuming that the request arrival process depends on both the value of the request counter and the location of a station on the buses. By taking these dependences, we can catch the real behavior of the DQDB stations, which is locationally dependent and unfair under heavy load traffic. Based on this model, we analyze the DQDB system with finite buffer by considering the request counter states and buffer states separately and obtain the throughput, mean packet delay and packet reject probability of individual stations. The throughput in individual stations matches that of simulation very well within the range of traffic up to the channel capacity. Also the delay and packet reject rate performance is good up to moderate traffic load. These numerical results reveal the properties of the location dependence and the unfairness of DQDB system under heavy load condition. The analytic results under heavy load traffic for a general DQDB system has not been reported till now. Therefore we conclude that our model and analysis are valid and effective.