The IEEE 1394 is a standard for the high performance serial bus interface. This standard has the isochronous transfer mode that is suitable for real-time applications and the asynchronous transfer mode for delay-insensitive applications. It can be used to construct a small-size local area network. We propose a queueing model for a network with this standard under some assumptions, and calculate the average waiting time of an asynchronous packet in the buffer in the steady state. We give some numerical results, along with validation by simulation, in order to evaluate its performance.

We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

Distributed domino effect-free checkpointing techniques can be divided into two categories: coordinated and communication-induced checkpointing. The former is inappropriate for mobile computing systems because it either forces every mobile host to take a new checkpoint or blocks the underlying computation during the checkpointing process. The latter makes every mobile host take the checkpoint independently. However, each mobile host may need to store multiple local checkpoints in stable storage. This investigation presents a novel three level synchronous checkpointing algorithm that combines the advantages of above two methods for mobile computing systems. The algorithm utilizes pre-synchronization, quasi-synchronization, and post-synchronization techniques and has the following merits: (1) Consistent global checkpoints can be ensured. (2) No mobile host is blocked during checkpointing. (3) Only twice the checkpoint size is required. (4) Power consumption is low. (5) The disconnection problem of mobile hosts can be resolved. (6) Very few mobile hosts in doze mode are disturbed. (7) It is simple and easy to implement. The proposed algorithm's numerical results are also provided in this work for comparison. The comparison reveals that our algorithm outperforms other algorithms in terms of checkpoint overhead, maintained checkpoints, power consumption, and disturbed mobile hosts.

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.

A multiport representation of the step junction of two circular dielectric waveguides of different size is given. Continuous spectral modes of the circular dielectric waveguide are discretized at a terminal plane by means of expressing their mode amplitudes in the form of infinite series of orthonormal Gaussian Laguerre function. Applying the mode matching technique, a multiport representation of the step junction is derived. Numerical examples are given where the results are tested for the conservation of power. Also the numerical results are compared with those from Marcuse's approximate methods.

A periodic approach introduced previously is applied to the TM wave scattering from a finite periodic surface. A mathematical relation is proposed to estimate the scattering amplitude from the diffraction amplitude for the periodic surface, where the periodic surface is defined as a superposition of surface profiles generated by displacing the finite periodic surface by every integer multiple of the period . From numerical examples, it is concluded that the scattering cross section for the finite periodic surface can be well estimated from the diffraction amplitude for a sufficiently large .

This paper introduces current-mode biquad using multiple current output operational transconductance amplifiers (OTAs) and grounded capacitors. The circuit configuration is obtained from a second-order integrator loop structure with loss-less and lossy integrators. The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. It is also made clear that the proposed circuit has very low sensitivities with respect to the circuit active and passive elements. An example is given together with simulated results by PSpice.

Near-optimality of subcodes of the cyclic Hamming codes is demonstrated on the binary additive channel whose noise process is the two-state homogeneous Markov chain, which is a model of bursty communication channels.

This document analyzes the characteristics of Waiting Time Jitter (WTJ) generated in High-bit-rate Digital Subscriber Lines (HDSL) systems transmitting non-uniform frames. It also derives the Fourier transform of the above WTJ.

The heterogeneous autonomous decentralized system technology offers a way to integrate different types of context-related autonomous decentralized (sub) systems into a coherent system. The aim of this research is to model and evaluate the communication capacity among the subsystems connected by communication gateways of a heterogeneous autonomous decentralized system. Failures of subsystems and communication gateways in the system are taken into account. We use graphs to represent the topologies of heterogeneous autonomous decentralized systems and use the residual connectedness reliability (RCR) to characterize the communication capacity among its subsystems connected by its gateways. This model enables us to share research results obtained in residual connectedness reliability study in graph theory. Not to our surprise, we learnt soon that computing RCR of general graphs is NP-hard. But to our surprise, there exist no efficient approximation algorithms that can give a good estimation of RCR for an arbitrary graph when both vertices and edges may fail. We proposed in this paper a simulation scheme that gave us good results for small to large graphs but failed for very large graphs. Then we applied a theoretical bounding approach. We obtained expressions for upper and lower bounds of RCR for arbitrary graphs. Both upper and lower bound expressions can be computed in polynomial time. We applied these expressions to several typical graphs and showed that the differences between the upper and lower bounds tend to zero as the sizes of graphs tend to infinite. The contributions of this research are twofold, we find an efficient way to model and evaluate the communication capacity of heterogeneous autonomous decentralized systems; we contribute an efficient algorithm to estimate RCR in general graph theory.

We have developed InGaP-channel field effect transistors (FETs) with high breakdown voltages that can be fabricated by using conventional GaAs FET fabrication processes. The buffer and barrier layers were also optimized for the realization of high-voltage operation. The InGaP-channel FET has an extremely high on-state drain-to-source breakdown voltage of over 40 V, and a gate-to-drain breakdown voltage of 55 V. This enabled high-voltage large-signal operation at 40 V. The third-order intermodulation distortion of the InGaP channel FETs was 10-20 dB lower than that of an equivalent GaAs-channel FET, due to the high operating voltage.

In this paper, we are concerned in obtaining multicast trees in packet-switched networks such as ATM nets, when there exist constraints on the packet (cell)-replication capabilities of the individual switching nodes. This problem can be formulated as the Steiner tree problem with degree bounds on the nodes, so we call it the Degree-Constrained Steiner Tree problem (DCST). Four heuristic algorithms are proposed: the first is a combined version of two well-known Steiner tree algorithms, heuristic Naive and the shortest path heuristic (SPH), and the second is a relaxation algorithm based on a mathematical formulation of the DCST, and the last two use a tree reconfiguration scheme based on the concept of 'logical link. ' We experimentally compare our algorithms with the previous ones in three respects; number of solved instances, objective value or tree cost, and computation time. The experimental results show that there are few instances unsolved by our algorithms, and the objective values are mostly within 5% of optimal. Computation times are also acceptable.

This paper has a dual purpose. First, it proposes a virtual path management model for ATM networks. The model unifies VPC overlay network configuration, VCC routing, and capacity allocation in a single framework. It accommodates multiple end-to-end offered traffics of various QoS requirements and traffic types. Especially, it also supports point-to-multipoint as well as point-to-point connections in a resource-efficient manner. The objective is to minimize the overall network resource cost. To do so, it pursues an optimal trade-off among the gains offered by ATM technology. The application of the proposed model is naturally extended to the multiprotocol label switching framework. Second, it proposes an efficient algorithm to solve the model. The mathematical formulation of such a unifying model typically involves a very large-scale intractable optimization which, treated by a straightforward method, requires excessive computational efforts. In this paper, we show how the computational structure of formulation can be exploited to tailor a solution method providing good solutions in dramatically reduced computational efforts.

This paper describes a cumulative distribution function (CDF) of edge direction for detecting road lanes. Based on the assumptions that there are no abrupt changes in the direction and location of road lanes and that the intensity of lane boundaries differs from that of the background, the CDF is formulated, which accumulates the edge magnitude for edge directions. The CDF has distinctive peak points at the vicinity of lane directions due to the directional and the positional continuities of a lane. To obtain lane-related information, we construct a scatter diagram by collecting edge pixels, of which the direction corresponds to the peak point of the CDF, then perform the principal axis-based line fitting for the scatter diagram. Because noises can cause many similar features appear or disappear in an image, to prevent false alarms or miss detection, a recursive estimator of the CDF was introduced, and also a scene understanding index (SUI) was formulated by the statistical parameters of the CDF. The proposed algorithm has been implemented in real time on video data obtained from a test vehicle driven on a typical highway.

In this paper, a novel three-port antenna structure, named 180 antenna hybrid, is proposed and demonstrated. This structure is composed of a Wilkinson power divider with the isolation resistor replaced by an aperture-coupled patch antenna. The equivalent series impedance of the antenna can be adjusted to the required one by properly choosing the dimensions of the patch and the coupling aperture. When a signal is fed to the balanced port of this antenna hybrid, the power is equally split, with equal phases, to the two unbalanced ports. No power is radiated out from the antenna. In the other hand, a signal received from the antenna will be split with equal power but 180 phase difference to the two unbalanced ports. The balanced port is an isolation port. The measurement results showed good agreement with the characteristics to be designed. Three applications of this 180 antenna hybrid are introduced, that is, a balanced mixer, an active transmitting antenna, and a dual-radiation-mode antenna array. The balanced mixer was constructed with diodes directly mounted on the two unbalanced ports of the antenna hybrid. The LO signal is fed from the balanced port and RF signal is received from the antenna. The active transmitting antenna was implemented with feedback configuration. The route from one of the unbalanced port to the balanced port of the antenna hybrid was used as the feedback path. A locking signal may be injected from the other unbalanced port. Finally, through a three-quarter-wavelength microstrip line, the balanced port of the antenna hybrid was connected to another aperture-coupled patch antenna to form a dual-radiation-mode antenna array. The in-phase and out-of-phase radiation patterns of this two-element array can be obtained from two unbalanced ports of the antenna hybrid, respectively.

Current-voltage characteristics of Cr-doped hydrogenated amorphous silicon-V (Cr/p+a-Si:H/V) analogue memory switching devices have been measured over a wide range of device resistance from several kilo-ohms to several hundred kilo-ohms, and over a temperature range from 13 K to 300 K. Both the bias and temperature dependence of the conductance show similar characteristics to that of metal-insulator heterogeneous materials (i.e. discontinuous or granular metallic films), which are analysed in terms of activated tunnelling mechanism. A modified filamentary structure for the Cr/p+a-Si:H/V switching devices is proposed. The influence of embedded metallic particles on memory switching is analysed and discussed.

In using a reverberation chamber for radiated immunity testing, it is important to determine the number of discrete steps through which the stirrer rotates and the number of probe locations for a given test volume in the chamber. This is because they affect the uniformity and calibration of the field in the test volume. We experimentally evaluated the effect of the numbers of stirrers and their steps on the field uniformity, and the effect of the number of probe locations on field calibration.

This paper proposes new recursive fixed-point smoother and filter using covariance information in linear continuous-time stochastic systems. To be able to treat the stochastic signal estimation problem, a performance criterion, extended from the criterion in the H filtering problem by introducing the stochastic expectation, is newly introduced in this paper. The criterion is transformed equivalently into a min-max principle in game theory, and an observation equation in the Krein spaces is obtained as a result. For γ2<, the estimation accuracies of the fixed-point smoother and the filter are superior to the recursive least-squares (RLS) Wiener estimators previously designed in the transient estimation state. Here, γ represents a parameter in the proposed criterion. This paper also presents the fixed-point smoother and the filter using the state-space parameters from the devised estimators using the covariance information.

The unidirectional transmission links such as broadcast satellite links and cable links are strongly demanding type of link to provide high bandwidth and ubiquitous Internet connectivity with lower cost. In order to provide an internet connectivity, the UDLs, unidirectional links, should be available for the IP service. However, since the current Internet routing and upper layer protocols assume the bi-directional link, the UDLs have been considered as unavailable links for the IP service. This paper proposes an architecture and a mechanism for the IP service over the UDL. The proposed system emulates the bi-directional connectivity between all nodes on the UDL, in order to use the dynamic routing protocol, the TCP/IP protocol, on the UDL system. Receiver uses a link layer tunneling mechanism to forward the IP datagrams to the Feed over an IP cloud, that is not directly connected to the UDL. This proposed architecture enables the dynamic routing capability for UDLs, as well as user applications, without any software modification.

Since each ATM virtual path (VP) contains bundles of virtual channels (VCs), a VP layer network can serve as a server layer and each VC layer network can be a client layer. Therefore the effective VC service provisioning depends completely on the reliability of the VP layer network. We propose the ATM virtual path (VP) management framework with dynamic routing and rerouting schemes in a hierarchical transport network. The routing algorithm aims to provide the globally optimal route in a hierarchical network environment from the perspectives of maximization of network resource utilization and satisfaction of the end user's QoS requirement. The rerouting algorithm guarantees network survivability in the event of network faults or performance degradations. We also propose the implementation model of the ATM virtual path network management system (VP-NMS). Lastly, we evaluate the routing and rerouting performance for a real network, the High Speed Information Network (HSIN) of Korea Telecom.