We have proposed a top-down design methodology for the RSFQ logic circuits based on the Binary Decision Diagram (BDD). In order to show the effectiveness of the methodology, we have designed a small RSFQ microprocessor based on simple architecture. We have compared the performance of the 8-bit RSFQ microprocessor with its CMOS version. It was found that the RSFQ system is superior in terms of the operating speed though it requires extremely large area. We have also implemented and tested a 1-bit ALU that is one of the important components of the microprocessor and confirmed its correct operation.

We report our studies on the spectral sensitivity of superconducting NbN thin-film single-photon detectors (SPD's) capable of GHz counting rates of visible and near-infrared photons. In particular, it has been shown that a NbN SPD is sensitive to 1.55-µm wavelength radiation and can be used for quantum communication. Our SPD's exhibit experimentally measured intrinsic quantum efficiencies from 20% at 800 nm up to 1% at 1.55-µm wavelength. The devices demonstrate picosecond response time (<100 ps, limited by our readout system) and negligibly low dark counts. Spectral dependencies of photon counting of continuous-wave, 0.4-µm to 3.5-µm radiation, and 0.63-µm, 1.33-µm, and 1.55-µm laser-pulsed radiations are presented for the single-stripe-type and meander-type devices.

We present a design framework of a high-end server based on Single-Flux-Quantum (SFQ) circuit technologies. The server proposed here has multiple microprocessors and memories, which are mounted on a single board or package and are connected each other by SFQ interconnection switches. The extremely large bandwidth up to 100 Gbps/channel in the interconnection will be realized because of high throughput nature of the SFQ circuits. SFQ memories or Josephson-CMOS hybrid memories are employed as the shared memory of the multiprocessor. The SFQ microprocessors are constructed based on the complexity-reduced (CORE) architecture, in which complexity of the system is eased in exchange for using a high clock rate of the SFQ circuits. The processor is so-called Java-processor that directly executes the Java Byte Codes. Assuming a proper advancement of the Nb/AlOx/Nb integrated circuit process technology, we have estimated that the power consumption of the server system including a cryocooler is reduced by a factor of twenty as compared to the future CMOS system with the same processor performance, while the SFQ system has 100 times of magnitude larger memory-processor bandwidth.

We have designed a torque magnetometer using a 60-kG split-type superconducting magnet. A balance torque compensates the torque acting on a sample in the magnetic field. The feedback circuit for a sample direction consists of an optical position sensor, a moving coil, and a PID controller. We measured the coil current to know a sample torque. The whole torque machinery is directly rotated by a stepping motor of angular resolution 0.0036. An advantage of the torque apparatus is a wide dynamic range up to 1000 dyncm. The sample temperature can be controlled between 4 K and 300 K.

Despite the enormous power of present-day computers, digital systems cannot respond to real-world events in real time. Biological systems, however, while being built with very slow chemical transistors, are very fast in such tasks like seeing, recognizing, and taking immediate actions. This paper discusses the issue of how we can build real-time intelligent systems directly on silicon. An intelligent VLSI system inspired by a psychological brain model is proposed. The system stores the past experience in the on-chip vast memory and recalls the maximum likelihood event to the current input based on the associative processor architecture. Although the system can be implemented in a CMOS digital technology, we are proposing here to implement the system using circuits operating in the analog/digital-merged decision making principle. Low-level processing is done in the analog domain in a fully parallel manner, which is immediately followed by a binary decision to yield answers in digital formats. Such a scheme would be very advantageous in achieving a high throughput computation under limited memory and computational resources usually encountered in mobile applications. Hardware-friendly algorithms have been developed for real-time image recognition using the associative processor architecture and some experimental results are demonstrated.

We propose a new decidable subclass of term rewriting systems (TRSs) for which strongly normalizing (SN) property is decidable. The new class is called almost orthogonal inverse finite path overlapping TRSs (AO-FPO-1-TRSs) and the class properly includes AO growing TRSs for which SN is decidable. Tree automata technique is used to show that SN is decidable for AO-FPO-1-TRSs.

This article describes simulation study on SQUID applications for Single-Flux-Quantum(SFQ) Logic Circuits. Here, a SQUID is compatible to a Quantum Flux Parametorn (QFP). Several new circuits based on a SQUID are investigated. A cascaded SQUID is proposed with the signal amplitude in the same order of an SFQ. An SFQ-pulse driving circuits with the new SQUID are successfully simulated. An SFQ trap which catches SFQs is newly proposed. Focusing on a circulating current of a segment in a Josephson transmission line (JTL), an SFQ-pulse is non-destructively detected by a SQUID. A conventional SQUID inserted in a JTL operates as a gate which controls SFQ-pulse transmission through it. Compatibility of SQUIDs and SFQ circuits is demonstrated.

High-end telecommunication systems in the larger nationwide networks of the next decade will require routers having a packet switching throughput capacity of over 10 Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. We propose a high-end router system architecture using single flux quantum (SFQ) technology. This system consists of semiconductor line card units and an SFQ switch card unit. The features of this switch card architecture are (1) using internal speedup architecture to reduce effective loads in the network, (2) using a packet switch scheduler to attain non-blocking characteristics. This architecture can expand the switching capacity to a level greater than tens of Tbps scale, keeping with non-blocking characteristics.

In this report, we propose a new bilateral floating resistor circuit having both positive and negative resistance values. The equivalent resistance of this floating resistor in CMOS technology can be changed by using controlled-voltages, which is an advantage over polysilicon or diffused resistor in the integrated circuit. Moreover the characteristics of the proposed circuit are independent of the threshold voltage. We have simulated the proposed circuit by using HSPICE. Finally, we have confirmed that the proposed circuit is useful as an analog component.

The mobile computing system is a set of functions on a distributed environment organized to support mobile hosts. In this environment, mobile hosts should be able to move without any constraints and should remain connected to the network even while moving. Also, they should be able to get necessary information regardless of their current location and time. Distributed mutual exclusion methods for supporting distributed algorithms have hitherto been designed for networks only with static hosts. However, with the emergence of mobile computing environments, a new distributed mutual exclusion method needs to be developed for integrating mobile hosts with underlying distributed systems. In the sense, many issues that should be considered stem from three essential properties of mobile computing system such as wireless communication, portability, and mobility. Thus far, distributed mutual exclusion methods for mobile computing environments were designed based on a token ring structure, which has the drawback of requiring high costs in order to locate mobile hosts. In this paper, we propose not only a distributed mutual exclusion method that can reduce such costs by structuring the entire system as a tree-based logical structure but also recovery schemes that can be applied when a node failure occurs. Finally, we evaluate the operation costs for the mutual exclusion scheme and the recovery scheme.

Phase-inversion between neighboring pulses appearing in carrier-suppressed return-to-zero pulses is effective in reducing the signal distortion due to chromatic dispersion and nonlinear effects. A generation method of the anti-phase pulses at 40 GHz is demonstrated by using semiconductor mode-locked lasers integrated with chirped gratings. Operation principle and pulse characteristics are described. Suppression of pulse distortion due to fiber dispersion is confirmed for generated anti-phase pulses. Repeaterless 150-km dispersion-shifted-fiber L-band transmission at 42.7 Gbit/s is demonstrated by using the pulse source.

Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)B-SbEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)B-SbEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.

This paper investigates the accepting powers of one-way alternating and deterministic multi-counter automata operating in realtime. We partially solve the open problem posed in [4], and show that for each k1, there is a language accepted by a realtime one-way deterministic (k+3)-counter automaton, but not accepted by any realtime one-way alternating k-counter automaton.

The stateless-based cache invalidation schemes for wireless environments can be categorized into either asynchronous or synchronous cache invalidation according to the broadcasting way of invalidation report. However, if the asynchronous cache invalidation scheme attempts to support local processing of read-only transaction, a critical problem may occur; the asynchronous invalidation reports provide no guarantee of waiting time for mobile transactions requesting commit. To solve this problem, the server in our approaches broadcasts two kind of messages, asynchronous invalidation report to reduce transaction latency and periodic guide message to avoid the uncertainty of waiting time for the next invalidation report. This paper presents a simulation-based analysis on the performance of the suggesting algorithms. The simulation experiments show that the local processing algorithms of read-only transaction based on asynchronous cache invalidation scheme get better response time than the algorithm based on synchronous cache invalidation scheme.

The explosive growth of World Wide Web usage is causing a number of performance problems, including slow response times, network congestion, and denial of service. Web site that has a huge number of accesses and requires high quality of services, such as a site offering hosting services, or content delivery services, usually uses a cache server to reduce the load on the original server offering the original content. To increase the throughput of the caching process and to improve service availability, multiple cache servers are often positioned in front of the original server. This requires a switch to direct incoming requests to one of the multiple cache servers. In this paper, we propose a routing algorithm for such a switch in front of clustered multiple cache servers and evaluate its performance by simulation. The results show that our routing algorithm is effective when content has request locality and a short period of validity, for example, news, map data, road traffic data, or weather information. We also identify points to consider when the proposed algorithm is applied to a real system.

In this paper we discuss the estimation of effort needed to update program codes according to given design specification changes. In the Object-Oriented incremental development (OOID), the requirement changes occur frequently and regularly. When a requirement change occurs, a design specification is changed accordingly. Then a program code is updated for given design specification change. In order to construct the development plan dynamically, a simple and fast estimation method of efforts for code updating is strongly required by both developers and managers. However, existing estimation methods cannot be applied to the OOID. We therefore try to propose a straightforward approach to estimate effort for code updating, which reflects the specific properties of the OOID. We list up following factors of the effort estimation for OOID: (1) updating activities consist of creation, deletion, and modification, (2) the target to be updated has four kinds of types (void type, basic type, library type, and custom type), (3) the degree of information hiding is classified into private, protected and public, and (4) the degree of inheritance affects updating efforts. We then propose a new formula E(P,σ) to calculate the efforts needed to update a program P according to a set of design specification changes σ. The formula E(P,σ) includes weighting parameters: Wupd, Wtype, Winf-h and Winht according to the characteristics (1), (2), (3) and (4), respectively. Finally, we conduct experimental evaluations by applying the formula E(P,σ) to actual project data in a certain company. The evaluation results statistically showed the validity of the proposed approach to some extent.

In this paper we addresses the problem of finding feasible solutions for the Group Multicast Routing Problem (GMRP). This problem is a generalization of the multicast routing problem whereby every member of the group is allowed to multicast messages to other members from the same group. The routing problem involves the construction of a set of low cost multicast trees with bandwidth requirements for all the group members in the network. We first prove that the problem of finding feasible solutions to GMRP is NP-complete. Following that we propose a new heuristic algorithm for constructing feasible solutions for GMRP. Simulation results show that our proposed algorithm is able to achieve good performance in terms of its ability of finding feasible solutions whenever one exist.

This paper describes the recent progress made in developing wavelength tunable semiconductor light sources for WDM applications. Wide and quasi-continuous wavelength tunings were investigated for a wavelength-selectable laser and a wavelength tunable distributed Bragg reflector (DBR) laser having a super structure grating (SSG). A wavelength-selectable laser consisting of a DFB laser array, a multi-mode interferometer (MMI), and a semiconductor optical amplifier (SOA) demonstrated a quasi-continuous tuning range of 46.9 nm by using temperature control. A wavelength-tunable DBR laser with SSG exhibited a quasi-continuous tuning range of 62.4 nm by using three tuning current controls. Wavelength stabilization was also demonstrated under the temperature variations of 5.

Breakthroughs in crystal growth and conductivity control of nitride semiconductors during last two decades have led to such developments as high-brightness blue and green light-emitting diodes and long-lived violet laser diodes and so on. All of these nitride-based devices are robust and the most environmentally-friendly ones available. They enable us to save tremendous amount of energy and will be key devices in advanced information technology. Further progress in the area of crystal growth and device engineering will open up new frontier devices based on nitride semiconductors. In this paper, the evolution of nitride-based light-emitting devices is reviewed and the key issues, which must be addressed for nitrides to be fully developed, are discussed.

Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.