We investigate a state dependent multicast routing scheme, called Least Load Multicast Routing (LLMR), for single rate loss networks. The algorithm is based on Least Load Routing (LLR) concept and the approach is to select the least loaded links for establishing connections. An analytical model for LLMR is developed. The accuracy of the analytical model is compared with the simulation results and is found to be very good. We also develop a simplified analytical model for fully symmetrical networks, which is also verified by comparing with simulation results.

This paper focuses on a multi-beam combining scheme for DS-CDMA systems, which has RAKE combiners in multiple overlapped beams, in order to increase the reverse link capacity of DS-CDMA. This scheme is a very attractive technique because the maximal ratio combining (MRC) is carried out in space and time domains. However, in a practical situation, since the terminals in own sector are not uniformly located, the interference levels in respective beams are different. Therefore, receivers at the base station do not achieve ideal combining. This paper proposes a multi-beam combining scheme for DS-CDMA systems using weighting factor based on interference level of each beam. A fast closed loop transmission power control (TPC) scheme for the multi-beam combining system is also proposed. It is confirmed by computer simulation that the proposed scheme has excellent performance in the reverse link even if terminals in own sector are not uniformly located.

In this paper, we investigate the performance characteristics of parallel switching architectures constructed by a stack of multistage switching networks. We first find that the performances of the previously proposed parallel switching architectures are much worse than the expected ones from analytic models which are based on the assumption that traffic is uniformly distributed at each stage of a switching network. We show that this phenomenon is closely related to a traffic-distribution capability of a parallel switching system and has a large influence on the performance. From these results, we then propose an architectural solution based on the Generalized Shuffle Network (GSN) and analyze its performance by proposing a new iterative analysis method. The proposed architecture uses self-routing and deflection routing, and inherently has a traffic-distribution capability to improve switch performances such as cell loss and delay in a cost-effective manner. From the comparison of simulation and analysis results, it is shown that the developed models are quite accurate in predicting the performance of a new parallel switching system.

In an ideal fiber grating having a uniform refractive index modulation, the reflection or the transmission spectrum is symmetric with equal amount of side lobes on both sides of the resonant wavelength of the fiber grating. It is observed that a long-period fiber grating made by a non-uniform UV laser beam through a uniform amplitude mask has an asymmetric transmission spectrum. The asymmetric characteristic is explained with Mach-Zehnder effect in the long-period fiber grating. The non-uniform UV laser beam makes also a non-uniform index modulation along the fiber core. Therefore, a beam coupled to a cladding mode at a section of the grating can be re-coupled to the core mode after passing a certain distance. The re-coupled beam makes Mach-Zehnder-like interference with the un-coupled core mode. However, it is presented that the asymmetric phenomenon can be overcome by scanning the UV laser beam along the fiber over the mask. The beam scanning method is able to suffer the same fluence of the UV laser beam on the fiber. Finally, a linearly chirped long-period fiber grating was made using the non-uniform UV laser beam. Due to the asymmetricity the chirping effect was not clearly observed. It is also presented that the beam scanning method could remove the asymmetric problem and recover the typical spectrum of the linearly chirped fiber grating.

The present paper discusses several promising application areas for optical data links based on high-performance vertical-cavity surface-emitting laser diodes (VCSELs). Both 850 and 980 nm emission wavelength devices realized in the GaAs-AlGaAs or InGaAs-AlGaAs material systems are considered. We show data transmission results of 10 Gb/s signals at 830 nm wavelength over a new high-bandwidth multimode silica fiber of up to 1.6 km length. The same fiber type is employed to demonstrate the first 40 Gb/s transport over 300 m distance by means of a 4-channel coarse wavelength-division multiplexing approach. A first 1 10 linear VCSEL array capable of 10 Gb/s per channel operation is presented for use in next generation parallel optical modules. To improve the singlemode emission characteristics for output power in the 5 mW range we introduce a new device concept incorporating a long monolithic cavity. For low-cost short-distance data links we investigate graded-index polymer optical fibers and report on up to 9 Gb/s transmission over a length of 100 m. Polymer waveguides are also used in an optical layer of a hybrid electrical-optical printed circuit board. Transmitted 10 Gb/s optical data over a prototype board show the potential of this new technology. Finally we present two-dimensional VCSEL arrays for highly parallel data transport on a CMOS chip level. Both 980 and 850 nm bottom emitting devices with modulation capabilities up to 12.5 Gb/s are discussed.

We have developed a new planar lightwave circuit (PLC) platform eliminating Si terraces for hybrid integrated optical modules. This PLC platform has the advantage of a lower fabrication cost than the conventional PLC platform with an Si terrace, because it does not require fabrication processes such as Si terrace forming and mechanical polishing. Using our new PLC platform structure, we fabricated a transceiver for optical access networks and an 8-channel multi-channel photoreceiver for wavelength division multiplexing (WDM) interconnection systems.

We propose a new conditional linearization based on left-right separated conditional term rewriting systems, in which the left-hand side and the right-hand side of a rewrite rule have separate variables. By developing a concept of weight decreasing joinability we first present a sufficient condition for the Church-Rosser property of left-right separated conditional term rewriting systems. Applying this result to conditional linearization, we next show sufficient conditions for the unique normal form property and the Church-Rosser property of non-duplicating (unconditional) term rewriting systems even if they are non-left-linear or overlapping.

The IETF Mobile IPv6 enables any IPv6 node to both cache the Care-of Address associated with a mobile node's home address, and to directly send packets addressed to a mobile node at the Care-of Address using the IPv6 routing header. Support for optimizing the route is built in as a fundamental part of the protocol. Several hierarchical schemes have been presented recently on top of the Mobile IPv6. These schemes separate micro-mobility from macro-mobility and exploit a mobile node's locality. They can reduce the number of signaling messages sent to a home network and improve hand-off performance. However, existing hierarchical schemes do not achieve route optimization. When external correspondent nodes send packets to a mobile node, these packets are intercepted by an intermediate mobility agent encapsulated and routed to the mobile node. In this paper, we propose a new hierarchical scheme that enables any correspondent node to cache two Care-of Addresses; the mobile node's temporary address and the intermediate mobility agent's address. Also, we introduce two lifetimes managing the two Care-of Addresses. Until the lifetime associated with the mobile node's temporary address expires, a correspondent node can send packets directly to the mobile node. If the lifetime expires but the lifetime associated with the intermediate mobility agent's address has not expired, the correspondent node sends packets to the intermediate mobility agent. This proposal can reduce delay in packet delivery and optimize routing. Furthermore, based on the mobility of a mobile node, we introduce more reduced frequency of binding update and longer period of the lifetimes than the existing hierarchical schemes. Therefore, our proposal can reduce the binding update bandwidth as well as the packet delivery bandwidth lower than those of the IETF IPv6 and the existing hierarchical schemes.

Due to the lack of support in mobility and quality of service, today's IP-based networks have some inherent limitations for delivering multimedia services in a mobile environment. In the past few years, these issues have been addressed in the research community and the resulting techniques are being standardised. However, these developments have been done in isolation and become incompatible with each other. In addition to these technical issues, the future infrastructure for charging and accounting mobile multimedia services is expected to be increasingly complicated. In this paper we present a home-proxy based framework which can facilitate the integration of mobility support and QoS management. Furthermore, it enables centralised accounting, which simplifies the cost recovery processes of roaming services. To prove the viability of our design, we have built and tested this framework on a DiffServ wide-area backbone using an MP3 streaming application.

One of the disadvantages of compressed data is their vulnerability, that is, even a single corrupted bit in compressed data may destroy the decompressed data completely. Therefore, Variable-to-Fixed length Arithmetic Coding, or VFAC, with error detecting capability is discussed. However, implementable error recovery method for compressed data has never been proposed. This paper proposes Burst Error Recovery Variable-to-Fixed length Arithmetic Coding, or BERVFAC, as well as Error Detecting Variable-to-Fixed length Arithmetic Coding, or EDVFAC. Both VFAC schemes achieve VF coding by inserting the internal states of the decompressor into compressed data. The internal states consist of width and offset of the sub-interval corresponding to the decompressed symbol and are also used for error detection. Convolutional operations are applied to encoding and decoding in order to propagate errors and improve error control capability. The proposed EDVFAC and BERVFAC are evaluated by theoretical analysis and computer simulations. The simulation results show that more than 99.99% of errors can be detected by EDVFAC. For BERVFAC, over 99.95% of l-burst errors can be corrected for l 32 and greater than 99.99% of other errors can be detected. The simulation results also show that the time-overhead necessary to decode the BERVFAC is about 12% when 10% of the received words are erroneous.

This work presents an analysis of IDDQ dependency on the primary current that flows through the bridging fault and driven gates current. A maximum primary current depends only on the test vectors which minimize channel resistances of transistors. The driven gates current generates when intermediate voltage occurs on the faulty node with creation current path between VDD and GND through the driven gates, and its value depends on circuit parameters such as transistor sizes and fan-in number of driven gates.

In this paper, we proposed two models, the full multiple MCS (Multicast Server) model and the hybrid multiple MCS model to support multiple MCS over a single large cluster in ATM (Asynchronous Transfer Mode) networks. Also, we presented two methods for MCS assignment which are known as 2PSPMT (2 Phase Shortest Path based on Multicast tree) and hybrid-2PSPMT, and evaluated its performance by simulation. When an ATM host requests joining a specific multicast group, the MARS (Multicast Address Resolution Server) designates a proper MCS among the multiple MCSs for the group member to minimize the average path delay between the sender and the group members. Each method for MCS assignment construct a 2-phase partial multicast tree based on the shortest path algorithm. We reduced the average path delay in the multicast tree using these methods with various cluster topologies and MCS distribution scenarios in addition to distributing the load among multiple MCSs.

The problem of finding a minimum-cast multicast tree (Steiner tree) is known as NP complete. Heuristic based algorithms for this problem to achieve good performance are usually time-consuming. In this paper, we propose a new strategy called tree-caching for efficient multicast connection setup in connection-oriented networks. In this scheme, the tree topologies that have been computed are cached in a database of the source nodes. This can reduce the connection establishment time for subsequent connection requests which have some common multicast members, by an efficient reuse of cached trees without having to re-run a multicast routing algorithm for the whole group. This method can provide an efficient way to eliminate, when ever possible, the expensive tree computation algorithm that has to be performed in setting up a multicast connection. We first formulate the problem of tree-caching and then propose a tree-caching algorithm to reduce the complexity of the tree computations when a new connection is to be established. Through simulations, we find that the proposed tree-caching strategy performs very well and can significantly reduce the computation complexity for setting up multicast connections.

Most natural images are well modeled as smoothed areas segmented by edges. The smooth areas can be well represented by a wavelet transform with high regularity and with fewer coefficients which requires highpass filters with some vanishing moments. However for the regions around edges, short highpass filters are preferable. In one recently proposed approach, this problem was solved by switching filter banks using longer filters for smoothed areas of the images and shorter filters for areas with edges. This approach was applied to lossy image coding resulting in a reduction of ringing artifacts. As edges were predicted using neighboring pixels, the nonlinear transforms made the decorrelation more flexible. In this paper we propose a time-varying filterbank and apply it to lossless image coding. In this scheme, we estimate the standard deviation of the neighboring pixels of the current pixel by solving the maximum likelihood problem. The filterbank is switched between three filter banks, depending on the estimated standard deviation.

FDMA/TDMA non-geostationary earth orbit satellite systems (Non-GEOS) generally require a pre-planned pool of radio resource, i.e., frequency and time slot plan (FTSP), for each gateway earth station (GES) prior to the real-time channel assignment by the multiple GES's sharing the resources harmoniously. The time-variant nature of those systems implies that a dynamic FTSP planning method is crucial to the operation to cope with the time-variant traffic demand and the inter-beam interference condition. This paper proposes and compares three algorithms (Serial-numbering, DP-based, and Greedy algorithms) mixed with two strategies (concentrated- and spread-types) for the resource allocation. The numerical evaluation demonstrates that Greedy algorithm with the spread-type strategy is very effective and promising with feasible calculation time for the FTSP generation.

Recently, Vatan, Roychowdhury and Anantram have presented two types of revised versions of the Calderbank-Shor-Steane code construction, and have also provided an exhaustive procedure for determining bases of quantum error-correcting codes. In this paper, we investigate the revised versions given by Vatan et al., and point out that there is no essential difference between them. In addition, we propose an efficient algorithm for searching for bases of quantum error-correcting codes. The proposed algorithm is based on some fundamental properties of classical linear codes, and has much lower complexity than Vatan et al.'s procedure.

This paper presents a new performance and routability-driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). The contribution of our work is to overcome one of the most critical limitations of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGA. To this end, we devised new routing density measures that are directly linked to the structure (switch block) of symmetrical FPGA, and utilize them consistently in global and detailed routings. With the use of the proposed accurate routing metrics, we developed a new routing algorithm called a reliable net decomposition-based routing which is very fast, and yet produces excellent routing results in terms of net/path delays and routability. An extensive experiment was carried out to show the effectiveness of our algorithm based on the proposed cost metrics. In summary, when compared to the best known results in the literature (TRACER-fpga_PR and SEGA), our algorithm has shown 31.9% shorter longest path delay and 23.0% shorter longest net delay even with about 9 times faster execution time.

In the culture of marine chlorellas, it is necessary to count the number in order to understand the condition of increase. For that propose, counting by the naked eye using the microscope has been used. However, this method requires a lot of time and work. We have developed the automatic chlorella counter using image processing and neural network. Its effectiveness is confirmed through the experiment.

This letter presents a new transformation technique of series solution to asymptotic solution for a perfectly conducting wedge illuminated by E-polarized plane wave. This transformation gives an analytic manipulation example of the Weber-Schafheitlin integral for diffraction problem.

A new architecture-based Dynamically Programmable Arithmetic Array processor (DPAA) is proposed for general purpose Digital Signal Processing applications. Parallelism and pipelining are achieved by using DPAA, which consists of various basic arithmetic blocks connected through a code-division multiple access bus interface. The proposed architecture poses 100% interconnection flexibility because connections are done virtually through code matching instead of physical wire connections. Compared to conventional multiplexing architectures, the proposed interconnection topology consumes less chip area and thus, more arithmetic blocks can be incorporated. A 16-bit prototype chip incorporating 10 multipliers and 40 other arithmetic blocks had been implemented into a 4.5 mm 4.5 mm chip with 0.6 µm CMOS process. DPAA also features its simple programmability, as numerical formula can be used to configure the processor without programming languages or specialized CAD tools.