We present a 60-GHz wireless through-repeater system based on self-heterodyne transmission scheme with the potential to optimize the carrier-to-interference and noise ratio (CINR) performance according to the transmission distance. The phase-noise degradation through a 60-GHz repeater link is not a serious concern when we employ the self-heterodyne transmission scheme. Multichannel interferences caused by third-order intermodulation distortions are efficiently suppressed by setting a high power ratio of LO carrier to RF signals in the self-heterodyne transmission. However, this high power ratio results in a lower carrier-to-noise ratio (CNR) and becomes unsuitable for improving link performance if the transmission distance increases. In order to facilitate a solution, we propose and make an embodiment of 60 GHz self-heterodyne transmitters that provide flexible control over the power ratio of LO to RF in a range of 10 dB ranges. With them, we successfully demonstrate terrestrial digital broadcasting signals on five channels and optimize their performance for wireless through-repeater applications.

In this paper, we present an efficient low power scan test technique which simultaneously reduces both average and peak power consumption. The selective scan chain activation scheme removes unnecessary scan chain utilization during the scan shift and capture operations. Statistical scan cell reordering enables efficient scan chain removal. The experimental results demonstrated that the proposed method constantly reduces the average and peak power consumption during scan testing.

A method was developed for deriving the approximate global optimum of a nonlinear objective function with multiple local optimums. The objective function is expanded into a linear wave coefficient equation, so the problem of maximizing the objective function is reduced to that of maximizing a quadratic function with respect to the wave coefficients. Because a wave function expressed by the wave coefficients is used in the algorithm for maximizing the quadratic function, the algorithm is equivalent to a full search algorithm, i.e., one that searches in parallel for the global optimum in the whole domain of definition. Therefore, the global optimum is always derived. The method was evaluated for various objective functions, and computer simulation showed that a good approximation of the global optimum for each objective function can always be obtained.

An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-µm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides non-intrusive analog circuit testing.

Many existing software reliability models (SRMs) are based on the assumption that fault correction activities take a negligible amount of time and resources, which is often invalid in real-life situations. Consequently, the estimated and predicted software reliability tends to be over-optimistic, which could in turn mislead management in related decision-makings. In this paper, we first make an in-depth analysis of real-life software testing process; then a Markovian SRM considering fault correction process is proposed. Parameter estimation method and software reliability prediction method are established. A numerical example is given which shows that by using the proposed model and methods, the results obtained tend to be more appropriate and realistic.

Routing in wireless ad hoc networks is a challenging issue because it dynamically controls the network topology and determines the network performance. Most of the available protocols are based on single-rate radio networks and they use hop-count as the routing metric. There have been some efforts for multirate radios as well that use transmission-time of a packet as the routing metric. However, neither the hop-count nor the transmission-time may be a sufficient criterion for discovering a high-throughput path in a multirate wireless ad hoc network. Hop-count based routing metrics usually select a low-rate bound path whereas the transmission-time based metrics may select a path with a comparatively large number of hops. The trade-off between transmission time and effective transmission range of a data rate can be another key criterion for finding a high-throughput path in such environments. In this paper, we introduce a novel routing metric based on the efficiency of a data rate that balances the required time and covering distance by a transmission and results in increased throughput. Using the new metric, we propose an on-demand routing protocol for multirate wireless environment, dubbed MR-AODV, to discover high-throughput paths in the network. A key feature of MR-AODV is that it controls the data rate in transmitting both the data and control packets. Rate control during the route discovery phase minimizes the route request (RREQ) avalanche. We use simulations to evaluate the performance of the proposed MR-AODV protocol and results reveal significant improvements in end-to-end throughput and minimization of routing overhead.

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.

A new technique to estimate the Poynting vector distribution from near-magnetic-field measurement is proposed. To calculate the Poynting vector, both electric and magnetic field should be known. In the proposed method, only magnetic-field measurement of three orthogonal axes is required. Electric field is estimated from the measured magnetic field by using the Maxwell's equation. The modified Yee cell is employed to estimate electric field from the measured magnetic field. Finally, the Poynting vector is calculated from the measured magnetic field and the estimated electric field. Since the proposed method enables us to understand propagation direction of electro-magnetic energy, it can be utilized to locate an emission source and to investigate a mechanism of undesired emission. Experiments are carried out to discuss the accuracy and to validate practical usefulness.

A method for reducing ground clutter contribution from ground penetrating radar (GPR) data is proposed for discrimination of landmines located in shallow depth. The algorithm of this method is based on the Matching Pursuit (MP) that is a technique for non-orthogonal signal decomposition using dictionary of functions. As the dictionary of function, a wave-based dictionary constructed by taking account of scattering mechanisms of electromagnetic (EM) wave by rough surfaces is employed. Through numerical simulations, performance of ground clutter reduction is evaluated. The results show that the proposed method has good performance and is effective for GPR data preprocessing for discrimination of shallowly buried landmines.

Since scan testing is not based on the function of the circuit, but rather the structure, it is considered to be both a form of over testing and under testing. Moreover, it is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper proposes a fault-dependent test generation method to detect specified fault models completely and to increase defect coverage as much as possible under the test length constraint. We present experimental results for MCNC'91 benchmark circuits to evaluate bridging fault coverage, transition fault coverage, and statistical delay quality level and to show the effectiveness of the proposed test generation method compared with a stuck-at fault-dependent test generation method.

In this research a new prediction algorithm based on a Fuzzy Mix of Filters (FMF) is developed. The use of a fuzzy mix is a good solution because it makes intuitive the difficult design task of combining several types of filters, so that the outputs of the filters that work closer to their optimal behavior have higher influence in the predicted values. Therefore the FMF adapts, according to the motion of the tracked object or target, the filter weights to reduce the estimation error. The paper develops the theory about the FMF and uses it for applications with hard real-time requirements. The improvement of the proposed FMF is shown in simulation and an implementation on a parallel processor (FPGA) is presented. As a practical application of the FMF, experimental results are provided for a visual servoing task.

Since traffic in IP access networks is less aggregated than in backbone networks, its variance could be significant and its distribution may be long-tailed rather than Gaussian in nature. Such characteristics make it difficult to forecast traffic volume in IP access networks for appropriate capacity planning. This paper proposes a traffic forecasting method that includes a function to control residual error distribution in IP access networks. The objective of the proposed method is to grasp the statistical characteristics of peak traffic variations, while conventional methods focus on average rather than peak values. In the proposed method, a neural network model is built recursively while weighting residual errors around the peaks. This enables network operators to control the trade-off between underestimation and overestimation errors according to their planning policy. Evaluation with a total of 136 daily traffic volume data sequences measured in actual IP access networks demonstrates the performance of the proposed method.

This paper presents unconditionally stable and conformal FDTD schemes which are based on the alternating-direction implicit finite difference time domain (ADI-FDTD) method for accurate modeling of perfectly electric conducting (PEC) objects. The proposed schemes are formulated within the framework of the matrix-vector notation of the finite integration technique (FIT), which allows a systematic and consistent extension of finite difference solution of Maxwell's equations on dual grids. As possible choices of second-order convergent conformal method, we apply the partially filled cell (PFC) and the uniformly stable conformal (USC) schemes for the ADI-FDTD method. The unconditional stability and the rates of convergence of the proposed conformal ADI-FDTD (CADI-FDTD) schemes are verified by means of numerical examples of waveguide problems.

Initial growth of GaP on Si substrates using metalorganic vapor phase epitaxy was studied. Si substrates were exposed to PH3 preflow for 15 s or 120 s at 830 after they were preheated at 925. Atomic force microscopy (AFM) revealed that the Si surface after preflow for 120 s was much rougher than that after preflow for 15 s. After 1.5 nm GaP deposition on the Si substrates at 830, GaP islands nucleated more uniformly on the Si substrate after preflow for 15 s than on the substrate after preflow for 120 s. After 3 nm GaP deposition, layer structures were observed on a fraction of Si surface after preflow for 15 s. Island-like structures remained on the Si surface after preflow for 120 s. After 6 nm GaP deposition, the continuity of GaP layers improved on both substrates. However, AFM shows pits that penetrated a Si substrate with preflow for 120 s. Transmission electron microscopy of a GaP layer on the Si substrate after preflow for 120 s revealed that V-shaped pits penetrated the Si substrate. The preflow for a long time roughened the Si surface, which facilitated the pit formation during GaP growth in addition to degrading the surface morphology of GaP at the initial growth stage. Even after 50 nm GaP deposition, pits with a density on the order of 107 cm-2 remained in the sample. A 50-nm-thick flat GaP surface without pits was achieved for the sample with PH3 preflow for 15 s. The PH3 short preflow is necessary to produce a flat GaP surface on a Si substrate.

In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.

This paper presents a wordline gating logic for reducing unnecessary BTB accesses. Partial bit of the branch predictor was simultaneously recorded in the middle of BTB to prevent further SRAM operation. Experimental results with embedded applications showed that the proposed mechanism reduces around 38% of BTB power consumption.

We propose a novel epidemic routing policy, named energy optimal epidemic routing, for delay tolerant networks (DTNs). By investigating the tradeoff between delay and energy, we found the optimal transmission range as well as the optimal number of infected nodes for the minimal energy consumption, given a delivery requirement, specifically delay bound and delivery probability to the destination. We derive an analytic model of the Binary Spraying routing to find the optimal values, describing the delay distributions with respect to the number of infected nodes.

In recent VLSI systems, signal propagation delays are requested to achieve the specifications with very high accuracy. In order to meet the specifications, the routing of a net often needs to be detoured in order to increase the routing delay. A routing method should utilize a routing area with obstacles as much as possible in order to realize the specifications of nets simultaneously. In this paper, a fast longer path algorithm that generates a path of a net in routing grid so that the length is increased as much as possible is proposed. In the proposed algorithm, an upper bound for the length in which the structure of a routing area is taken into account is used. Experiments show that our algorithm utilizes a routing area with obstacles efficiently.

In this paper, we propose a routing method for 2-layer ball grid array packages that generates a routing pattern satisfying a design rule. In our proposed method, the routing structure on each layer is restricted while keeping most of feasible patterns to efficiently obtain a feasible routing pattern. A routing pattern that satisfies the design rule is formulated as a mixed integer linear programming. In experiments with seven data, we obtain a routing pattern such that satisfies the design rule within a practical time by using a mixed integer linear programming solver.

In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (p) and the overall numbers of sleep gates (gate count, N) are considered, and the sum of the product of p and N is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.