MapReduce and its open software implementation Hadoop are now widely deployed for big data analysis. As MapReduce runs over a cluster of massive machines, data transfer often becomes a bottleneck in job processing. In this paper, we explore the influence of data transfer to job processing performance and analyze the mechanism of job performance deterioration caused by data transfer oriented congestion at disk I/O and/or network I/O. Based on this analysis, we update Hadoop's Heartbeat messages to contain the real time system status for each machine, like disk I/O and link usage rate. This enhancement makes Hadoop's scheduler be aware of each machine's workload and make more accurate decision of scheduling. The experiment has been done to evaluate the effectiveness of enhanced scheduling methods and discussions are provided to compare the several proposed scheduling policies.

In this paper, a 97-mW 8-phase CMOS voltage-controlled oscillator (VCO) and dividers covering the entire VCO oscillation range for a 134-GHz phase-locked loop (PLL) synthesizer are presented. The dividers have two injection-locked frequency dividers (ILFDs), one with and one without an inductor, and a pulse-swallowing counter with a differential dual-modulus prescaler. The VCO has a fundamental oscillation frequency range of 131.8 GHz to 134.3 GHz, achieved by controlling the back-gate voltage, which is also used to tune the locking range of divide-by-2 and divide-by-3 dividers. The ratio between the measured VCO oscillation frequencies and output frequencies of dividers is in good agreement with the target ratio. This indicates that the dividers covered the entire VCO oscillation range. We fabricated the VCO and dividers with a chip core area of 180 µm × 100 µm implemented in a 65-nm CMOS process. The total power consumption was 97 mW at a 1.2-V supply voltage.

This paper provides a method based on electromagnetic (EM) analysis to predict conducted currents in the bulk current injection (BCI) test system for automotive components. The BCI test system is comprised of an injection probe, equipment under test (EUT), line impedance stabilization networks (LISNs), wires and an electric load. All components are modeled in full-wave EM analysis. The EM model of the injection probe enables us to handle multi wires. By using the transmission line theory, the BCI setup model is divided into several parts in order to reduce the calculation time. The proposed method is applied to an actual BCI setup of an automotive component and the simulated common mode currents at the input terminals of EUT have a good accuracy in the frequency range of 1-400MHz. The model separation reduces the calculation time to only several hours.

This paper presents an information hiding method for DNA steganography with which a massive amount of data can be hidden in a noncoding strand. Our method maps the encrypted data to the DNA sequence using a numerical mapping table, before concealing it in the noncoding sequence using a secret key comprising sector length and the random number generator's seed. Our encoding algorithm is sector-based and reference dependent. Using modular arithmetic, we created a unique binary-base translation for every sector. By conducting a simulation study, we showed that our method could preserve amino acid information, extract hidden data without reference to the host DNA sequence, and detect the position of mutation error. Experimental results verified that our method produced higher data capacity than conventional methods, with a bpn (bit-per-nucleotide) value that ranged from approximately 1-2, depending on the selected sector length. Additionally, our novel method detected the positions of mutation errors by the presence of a parity base in each sector.

An adaptively phase-shift controlled self-injection locked VCO is described. A self-injection locking technique is effective to reduce phase noise. However, a conventional self-injection locked VCO has drawbacks of discontinuous frequency sweep which means narrow bandwidth, and large variation of phase noise. Our proposed adaptively phase-shift controlled self-injection locked VCO overcomes these drawbacks by detecting phase-shift of the self-injection feedback and controlling the phase-shift depending on sweep of the oscillation frequency. This paper describes analysis of relationships between the discontinuity and feedback phase-shift of the self-injection locked VCO. In addition, a VCO-IC which includes a Ka-band VCO and a phase detector is designed and fabricated in 0.18um SiGe BiCMOS technology. Measurement results of the proposed self-injection locked VCO using the fabricated IC show the improvement to the drawbacks. In the proposed self-injection locked VCO, the oscillation frequency sweep is continuous and the phase noise variation is less than 5 dB.

We address a robust algorithm for the interference-plus-noise covariance matrix reconstruction (RA-INCMR) against random arbitrary steering vector mismatches (RASVMs) of the interferences, which lead to substantial degradation of the original INCMR beamformer performance. Firstly, using the worst-case performance optimization (WCPO) criteria, we model these RASVMs as uncertainty sets and then propose the RA-INCMR to obtain the robust INCM (RINCM) based on the Robust Capon Beamforming (RCB) algorithm. Finally, we substitute the RINCM back into the original WCPO beamformer problem for the sample covariance matrix to formulate the new RA-INCM-WCPO beamformer problem. Simulation results demonstrate that the performance of the proposed beamformer is much better than the original INCMR beamformer when there exist RASVMs, especially at low signal-to-noise ratio (SNR).

In this paper, VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder is presented. The adoption of new coding tools in PDec, such as Advanced Motion Vector Prediction (AMVP), increases the VLSI hardware realization overhead and memory bandwidth requirement, especially for 8K UHDTV application. We propose four techniques for these challenges. Firstly, this work unifies MV and BS parameter decoders for line buffer memory sharing. Secondly, to support high throughput, we propose the top-level CU-adaptive pipeline scheme by trading off between implementation complexity and performance. Thirdly, PDec process engine with optimizations is adopted for 43.2k area reduction. Finally, PU-based coding scheme is proposed for 30% DRAM bandwidth reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support real-time decoding for 7680x4320@60fps application at 249MHz in the worst case.

In deep-submicron era, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register architectures (RDR architectures) have been proposed to cope with this problem. In this paper, we propose a high-level synthesis algorithm using operation chainings which reduces the overall latency targeting RDR architectures. Our algorithm consists of three steps: The first step enumerates candidate operations for chaining. The second step introduces maximal chaining distance (MCD), which gives the maximal allowable inter-island distance on RDR architecture between chaining candidate operations. The last step performs list-scheduling and binding simultaneously based on the results of the two preceding steps. Our algorithm enumerates feasible chaining candidates and selects the best ones for RDR architecture. Experimental results show that our proposed algorithm reduces the latency by up to 40.0% compared to the original approach, and by up to 25.0% compared to a conventional approach. Our algorithm also reduces the number of registers and the number of multiplexers compared to the conventional approaches in some cases.

Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same.

Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor.

In this paper, we propose Affine Combination Lattice Algorithm (ACLA) as a new lattice-based adaptive notch filtering algorithm. The ACLA makes use of the affine combination of Regalia's Simplified Lattice Algorithm (SLA) and Lattice Gradient Algorithm (LGA). It is proved that the ACLA has faster convergence speed than the conventional lattice-based algorithms. We conduct this proof by means of theoretical analysis of the mean update term. Specifically, we show that the mean update term of the ACLA is always larger than that of the conventional algorithms. Simulation examples demonstrate the validity of this analytical result and the utility of the ACLA. In addition, we also derive the step-size bound for the ACLA. Furthermore, we show that this step-size bound is characterized by the gradient of the mean update term.

In recent years, applications of complex-valued neural networks have become wide spread. Quaternions are an extension of complex numbers, and neural networks with quaternions have been proposed. Because quaternion algebra is non-commutative algebra, we can consider two orders of multiplication to calculate weighted input. However, both orders provide almost the same performance. We propose hybrid quaternionic Hopfield neural networks, which have both orders of multiplication. Using computer simulations, we show that these networks outperformed conventional quaternionic Hopfield neural networks in noise tolerance. We discuss why hybrid quaternionic Hopfield neural networks improve noise tolerance from the standpoint of rotational invariance.

This paper considers a method for constructing good high-rate punctured convolutional codes through dual codes. A low-rate R=1/n convolutional code has a dual code identical to a punctured convolutional code with rate R=(n-1)/n. This implies that a low-rate R=1/n convolutional code encoder can help the search of punctured convolutional code encoders. This paper provides the procedures that obtain all the useful dual code encoders to a given CC with rate R=1/n easily, and the best PCC encoder with rate R=(n-1)/n among the encoders we derive from all the obtained dual code encoders. This paper also shows an example of the PCC the procedures obtain from some CC.

With the development and diverse use of wireless radio terminals, it is necessary to estimate the specific absorption rate (SAR) of the human body from such devices under various exposure situations. In particular, tablet computers may be used for a long time while placed near the abdomen. There has been insufficient evaluation of the SAR for the human body from tablet computers. Therefore, we investigated the SAR of various configurations of a commercial tablet computer using a numerical model with the anatomical structures of Japanese males and females, respectively. We find that the 10-g-averaged SAR of the tablet computer is strongly altered by the tablet's orientation, i.e., from -7.3dB to -22.6dB. When the tablet computer is moved parallel to the height direction, the relative standard deviations of the 10-g averaged SAR for the male and female models are within 40%. In addition, those for the different tilts of the computer are within 20%. The fluctuations of the 10-g-averaged SAR for the seated human models are within ±1.5dB in all cases.

In this work, a computationally-efficient modeling approach is developed to predict the electromagnetic noise induced in the terminal units of random bundles of twisted-wire pairs mounted onboard spacecraft. The proposed model combines the results of a preliminary fullwave simulation, aimed at evaluating the electromagnetic field inside the space vehicle's metallic body, with a stochastic model of a random bundle, based on multiconductor transmission line (MTL) theory. Model assessment versus measurement data obtained characterizing real wiring harness in a full-scale satellite mock-up demonstrates the large sensitivity (up to 40 decibels) of the induced noise levels to different bundle configurations, and corroborates the effectiveness of the proposed simplified modeling strategy for estimating the modal noise voltages induced in the terminal units.

One of the most important processes in cellular-assisted device-to-device (D2D) communications is device discovery, which decides whether two devices are located close to each other. The discovery process is performed by devices periodically transmitting discovery signals so that neighbor devices can receive them to recognize their proximate physical presence. While a fixed set of discovery parameters are used regardless of devices in most of the existing works, discovery periods are not necessarily the same for all devices, as they can be set differently depending on their channel conditions and operational environments, e.g., the mobile speeds. In this paper, we present an optimization framework to determine the discovery periods for individual devices in cellular-assisted D2D communication systems. We consider two different types of optimization problems, taking the different user velocities into account: minimizing the average number of undiscovered device pairs, and minimizing the number of discovery signal transmissions while maintaining the average number of undiscovered device pairs for each device less than a pre-specified threshold. We present analytical and simulation results to demonstrate that short discovery periods can be beneficial to high-mobility devices, while longer discovery periods are allowed for devices with lower velocities.

Delayed correlation has been used to detect orthogonal frequency division multiplexing symbols with cyclic prefix in spectrum sensing. Because of the frequency offset, the outputs of the delayed correlation do not lie only on the real axis of a complex plane. Therefore, the absolute value of the outputs of the delayed correlation is employed. Furthermore, with the use of a filter bank, the number of the outputs of the delayed correlators increases and the averaging over the outputs decreases the noise variance. This paper proposes a new delayed correlation scheme that uses a filter bank and employs the absolute of the outputs of delayed correlation. The proposed scheme improves the probability of detection as the number of the branches of the delayed correlators increases. In the case of 6 branches, the proposed scheme reduces the required sample energy by 1dB the probability of detection of 0.9.

Microwave imaging techniques, particularly for synthetic aperture radar (SAR), produce high-resolution terrain surface images regardless of the weather conditions. Focusing on a feature of complex SAR images, coherent change detection (CCD) approaches have been developed in recent decades that can detect invisible changes in the same regions by applying phase interferometry to pairs of complex SAR images. On the other hand, various techniques of polarimetric SAR (PolSAR) image analysis have been developed, since fully polarimetric data often include valuable information that cannot be obtained from single polarimetric observations. According to this background, various coherent change detection methods based on fully polarimetric data have been proposed. However, the detection accuracies of these methods often degrade in low signal-to-noise ratio (SNR) situations due to the lower signal levels of cross-polarized components compared with those of co-polarized ones. To overcome the problem mentioned above, this paper proposes a novel CCD method by introducing the Pauli decomposition and the weighting of component with their respective SNR. The experimental data obtained in anechoic chamber show that the proposed method significantly enhances the performance of the receiver operation characteristic (ROC) compared with that obtained by a conventional approach.

The authors have been researching on reducing the power consumption of microprocessors, and developed a low-power processor called “Geyser” by applying power gating (PG) function to the individual functional units of the processor. PG function on Geyser reduces the power consumption of functional units by shutting off the power voltage of idle units. However, the energy overhead of switching the supply voltage for units on and off causes power increases. The amount of the energy overhead varies with the behavior of each functional unit which is influenced by running application, and also with the core temperature. It is therefore necessary to switch the PG function itself on or off according to the state of the processor at runtime to reduce power consumption more effectively. In this paper, the authors propose a PG control method to take the power overhead into account by the operating system (OS). In the proposed method, for achieving much power reduction, the OS calculates the power consumption of each functional unit periodically and inhibits the PG function of the unit whose energy overhead is judged too high. The method was implemented in the Linux process scheduler and evaluated. The results show that the average power consumption of the functional units is reduced by up to 17.2%.

To eliminate CAMs from the load/store queues, several techniques to detect memory access order violation with hash filters composed of RAMs have been proposed. This paper proposes a technique with parallel counting Bloom filters (PCBF). A Bloom filter has extremely low false positive rates owing to multiple hash functions. Although some existing researches claim the use of Bloom filters, none of them make mention to multiple hash functions. This paper also addresses the problem relevant to the variety of access sizes of load/store instructions. The evaluation results show that our technique, with only 2720-bit Bloom filters, achieves a relative IPC of 99.0% while the area and power consumption are greatly reduced to 14.3% and 22.0% compared to a conventional model with CAMs. The filter is much smaller than usual branch predictors.