We present a new framework for embedding holographic halftone watermarking data into images by fusion of scale-related wavelet coefficients. The halftone watermarking image is obtained by using error-diffusion method and converted into Fresnel hologram, which is considered to be the initial password. After encryption, a scrambled watermarking image through Arnold transform is embedded into the host image during the halftoning process. We characterize the multi-scale representation of the original image using the discrete wavelet transform. The boundary information of the target image is fused by correlation of wavelet coefficients across wavelet transform layers to increase the pixel resolution scale. We apply the inter-scale fusion method to gain fusion coefficient of the fine-scale, which takes into account both the detail of the image and approximate information. Using the proposed method, the watermarking information can be embedded into the host image with recovery against the halftoning operation. The experimental results show that the proposed approach provides security and robustness against JPEG compression and different attacks compared to previous alternatives.

Barrel distortion is a critical problem that can hinder the successful application of wide-angle cameras. This letter presents an implementation method for fast correction of the barrel distortion. In the proposed method, the required scaling factor is obtained by interpolating a mapping polynomial with a non-uniform spline instead of calculating it directly, which reduces the number of computations required for the distortion correction. This reduction in the number of computations leads to faster correction while maintaining quality: when compared to the conventional method, the reduction ratio of the correction time is about 89%, and the correction quality is 35.3 dB in terms of the average peak signal-to-noise ratio.

The paper proposes an algorithm to expose spliced photographs. Firstly, a graph-based segmentation, which defines a predictor to measure boundary evidence between two neighbor regions, is used to make greedy decision. Then the algorithm gets prediction error image using non-negative linear least-square prediction. For each pair of segmented neighbor regions, the proposed algorithm gathers their statistic features and calculates features of gray level co-occurrence matrix. K-means clustering is applied to create a dictionary, and the vector quantization histogram is taken as the result vector with fixed length. For a tampered image, its noise satisfies Gaussian distribution with zero mean. The proposed method checks the similarity between noise distribution and a zero-mean Gaussian distribution, and follows with the local flatness and texture measurement. Finally, all features are fed to a support vector machine classifier. The algorithm has low computational cost. Experiments show its effectiveness in exposing forgery.

In this letter, we propose a new semantic parts learning approach to address the object detection problem with only the bounding boxes of object category labels. Our main observation is that even though the appearance and arrangement of object parts might have variations across the instances of different object categories, the constituent parts still maintain geometric consistency. Specifically, we propose a discriminative clustering method with sparse representation refinement to discover the mid-level semantic part set automatically. Then each semantic part detector is learned by the linear SVM in a one-vs-all manner. Finally, we utilize the learned part detectors to score the test image and integrate all the response maps of part detectors to obtain the detection result. The learned class-generic part detectors have the ability to capture the objects across different categories. Experimental results show that the performance of our approach can outperform some recent competing methods.

This paper proposes an updating state dependent disturbance observer (USDDOB) to reject position dependent disturbances when parameters vary slowly, and input and output are time-delayed. To reject the effects of resultant slowly-varying position dependent disturbances, the USDDOB uses the control method of the state dependent disturbance observer (SDDOB) and time-invariance approximation. The USDDOB and a main proportional integral (PI) controller constitute a robust controller. Simulations and experiments using a 1-degree-of-freedom (1-DOF) tilted planar robot show the effectiveness of the proposed method.

In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.

As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.

Multiple-input multiple-output (MIMO) transmission is attracting interest for increasing the transmission rates of wireless systems. This paper surveys MIMO transmission technology from the viewpoints of transmission methods, access control schemes, and total transmission efficiency. We consider wireless local area networks (WLAN) systems that use MIMO technology; moreover, we focus on multiuser MIMO (MU-MIMO) technology, which will be introduced in next-generation WLAN systems such as IEEE802.11ac. This paper explains the differences in the detailed access control procedures for MIMO and MU-MIMO transmission, including channel state information (CSI) acquisition. Furthermore, the issues related to CSI feedback and solutions are also discussed. Related works on the medium access control (MAC) protocol in MIMO/MU-MIMO transmission are introduced. In addition, the throughput performance using MIMO/MU-MIMO transmission is evaluated considering an IEEE802.11ac-based WLAN system. From the numerical evaluation, it is shown that the overhead due to CSI feedback from the user terminals to the base station causes a decrease in the throughput. We verified that implicit beamforming, which eliminates CSI feedback, is effective for solving this issue.

This paper presents a method for evaluating the maximum bit error probability (BEP) of a digital communication system subjected to interference by measuring the amplitude probability distribution (APD) of the interfering noise. Necessary conditions for the BEP evaluation are clarified both for the APD measuring receiver and the communication receiver considered. A method of defining emission limits is presented in terms of APD so that the worst BEP of a communication system does not exceed a required permissible value. The methods provide a theoretical basis for a wide variety of applications such as emission requirements in compliance testing, dynamic spectrum allocations, characterization of an electromagnetic environment for introducing new radio systems, and evaluation of intra-system interference.

This paper describes circuit design and measurement results of a newly proposed GaAs-HBT step-gain amplifier configuration and its application to a 3.3-3.6 GHz WiMAX power amplifier module for use in customer premises equipment. The step-gain amplifier implemented using only a usual HBT process is based on a current-mirror-based, base-collector diode switches and a passive attenuator core for the purpose of bypassing a power-gain stage. The stage allows an individual design approach in terms of gain and attenuation levels as well as large operating current reduction in the attenuation state. To confirm the effectiveness of the proposed step-gain amplifier, a prototype of the amplifier was designed and fabricated, and then a WiMAX power amplifier module was also designed and fabricated as an application example of the proposed configuration to an amplifier product. Measurements are as follows. For a 3.5-V power supply and a 3.5-GHz non-modulated signal, the step-gain amplifier delivers 23.7 dBm of 1-dB gain compressed output power and 10.7 dB of linear gain in the amplification state. In the attenuation state, the amplifier exhibits 21 dBm of 1-dB gain expanded input power, -9.7 dB of gain, and 15 mA of current dissipation while keeping the gain stage switched off and maintaining input and output return loss of less than -10 dB at a 3.5-GHz band. The WiMAX amplifier operating with a 5-V supply voltage and a 64-QAM modulated signal is capable of delivering a 28.5-dBm linear output power, a 37-39 dB gain, and 15% of PAE over a wide frequency range from 3.3 to 3.6 GHz in the high-gain state while keeping error vector magnitude as low as 2.5%. This amplifier, which incorporates the proposed step-gain configuration into its interstage, enables a 24-dB gain reduction and a 45-mA large quiescent current reduction in the low-gain state.

This invited paper aims to present an overview of our recent research and development (R&D) of advanced microwave planar filters, in particular with miniaturization and/or electronically tunable/ reconfigurable functionalities, which are in demand for future communication/radar systems as well as emerging wireless applications.

Graphical User Interfaces (GUIs) are critical for the security, safety and reliability of software systems. Injection attacks, for instance via SQL, succeed due to insufficient input validation and can be avoided if contract-based approaches, such as Design by Contract, are followed in the software development lifecycle of GUIs. This paper proposes a model-based testing approach for detecting GUI data contract violations, which may result in serious failures such as system crash. A contract-based model of GUI data specifications is used to develop test scenarios and to serve as test oracle. The technique introduced uses multi terminal binary decision diagrams, which are designed as an integral part of decision table-augmented event sequence graphs, to implement a GUI testing process. A case study, which validates the presented approach on a port scanner written in Java programming language, is presented.

This paper demonstrates the resonant power supply noise reduction effects of STO thin film decoupling capacitors, which are embedded in interposers. The on-interposer STO capacitor consists of SrTiO2 whose dielectric constant is about 20 and is sandwitched by Cu films in an interposer. The on-interposer STO capacitors are directly connected to the LSI PADs so that they provide large decoupling capacitance without package leadframe/bonding wire inductance, resulting in the reduction of the resonant power supply noise. The measured power supply waveforms show significant reduction of the power supply noise, and the Shmoo plots also show the contribution of the STO capacitors to the robust operations of LSIs.

Power supply noise generated by integrated circuits is one of the major sources of electromagnetic radiation from printed circuit boards (PCB). The reduction of power supply noise can be realized by means of devices that bypass the current among power supply planes, such as bypass capacitors and ground vias. In the present work, the effect of current bypass devices on the far field radiation from multilayer PCBs is represented in terms of the ratio between the far field after and before their introduction, and it is estimated by means of the power transported by the ‘radiation effective forward wave’ in infinite power supply planes. This approach is computationally very efficient and yelds improved EMC designs for power supply planes in realistic PCBs, for example by selecting the position of stitching ground vias. The results are confirmed by a comparison with commercial tools. Forward wave analysis can be used also to study the vertical distribution of the power supply noise in multilayer PCBs. This allows to understand some important noise propagation mechanisms that are related to power and signal integrity as well, and to take low-cost countermeasures at early stage of PCB design.

In 1919 the Department of Electrical Engineering (EE) was established in Tohoku University (at that time, Tohoku Imperial University). In this Department a growing tendency towards research featured in science and technology for electrical communication. Great efforts made in these fields produced pioneering studies such as those of the Yagi-Uda antenna and slotted-anode type magnetrons in the late 1920s. The purpose of this article is to introduce the history of development of microwave electron-tube at Tohoku University, which was started with the Okabe's magnetron.

The coarse-grained reconfigurable architecture (CGRA) is a promising computing platform that provides both high performance and high power-efficiency. The computation-intensive portions of an application (e.g. loop nests) are often mapped onto CGRA for acceleration. However, mapping loop nests onto CGRA efficiently is quite a challenge due to the special characteristics of CGRA. To optimize the mapping of loop nests onto CGRA, this paper makes three contributions: i) Establishing a precise performance model of mapping loop nests onto CGRA, ii) Formulating the loop nests mapping as a nonlinear optimization problem based on polyhedral model, iii) Extracting an efficient heuristic algorithm and building a complete flow of mapping loop nests onto CGRA (PolyMAP). Experiment results on most kernels of the PolyBench and real-life applications show that our proposed approach can improve the performance of the kernels by 27% on average, as compared to the state-of-the-art methods. The runtime complexity of our approach is also acceptable.

This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.

For systems with a delay in the input, the predictor method has been often used in state feedback controllers for system stabilization or regulation. In this letter, we show that for a chain of integrators with even an unknown input delay, a much simpler and memoryless controller is a good candidate for system regulation. With an adaptive gain-scaling factor, the proposed state feedback controller can deal with an unknown time-varying delay in the input. An example is given for illustration.